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DS90LV110TMTC PDF预览

DS90LV110TMTC

更新时间: 2024-11-17 11:11:39
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动光电二极管逻辑集成电路
页数 文件大小 规格书
18页 686K
描述
1:10 LVDS 数据/时钟分配器 | PW | 28 | -40 to 85

DS90LV110TMTC 技术参数

生命周期:Not Recommended零件包装代码:SSOP
包装说明:TSSOP, TSSOP28,.25针数:28
Reach Compliance Code:not_compliantECCN代码:5A991.B.1
HTS代码:8542.39.00.01风险等级:6.9
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:155059Samacsys Pin Count:28
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Small Outline Packages
Samacsys Footprint Name:PW(R-PDSO-G28)Samacsys Released Date:2015-04-16 09:48:08
Is Samacsys:N系列:90LV
输入调节:DIFFERENTIALJESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:9.7 mm
负载电容(CL):5 pF逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:28
实输出次数:10最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP28,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TUBE
峰值回流温度(摄氏度):235电源:3.3 V
最大电源电流(ICC):195 mAProp。Delay @ Nom-Sup:3.6 ns
传播延迟(tpd):3.6 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.091 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

DS90LV110TMTC 数据手册

 浏览型号DS90LV110TMTC的Datasheet PDF文件第2页浏览型号DS90LV110TMTC的Datasheet PDF文件第3页浏览型号DS90LV110TMTC的Datasheet PDF文件第4页浏览型号DS90LV110TMTC的Datasheet PDF文件第5页浏览型号DS90LV110TMTC的Datasheet PDF文件第6页浏览型号DS90LV110TMTC的Datasheet PDF文件第7页 
DS90LV110T  
www.ti.com  
SNOS522I JANUARY 2001REVISED APRIL 2013  
DS90LV110T 1 to 10 LVDS Data/Clock Distributor  
Check for Samples: DS90LV110T  
1
FEATURES  
DESCRIPTION  
DS90LV110 is a 1 to 10 data/clock distributor utilizing  
LVDS (Low Voltage Differential Signaling) technology  
for low power, high speed operation. Data paths are  
fully differential from input to output for low noise  
generation and low pulse width distortion. The design  
allows connection of 1 input to all 10 outputs. LVDS  
I/O enable high speed data transmission for point-to-  
point interconnects. This device can be used as a  
high speed differential 1 to 10 signal distribution /  
fanout replacing multi-drop bus applications for higher  
speed links with improved signal quality. It can also  
be used for clock distribution up to 400MHz.  
2
Low jitter 800 Mbps fully differential data path  
145 ps (typ) of pk-pk jitter with PRBS = 2231  
data pattern at 800 Mbps  
Single +3.3 V Supply  
Less than 413 mW (typ) total power dissipation  
Balanced output impedance  
Output channel-to-channel skew is 35ps (typ)  
Differential output voltage (VOD) is 320mV (typ)  
with 100Ω termination load.  
LVDS receiver inputs accept LVPECL signals  
Fast propagation delay of 2.8 ns (typ)  
Receiver input threshold < ±100 mV  
28 lead TSSOP package  
The DS90LV110 accepts LVDS signal levels,  
LVPECL levels directly or PECL with attenuation  
networks.  
The LVDS outputs can be put into TRI-STATE by use  
of the enable pin.  
Conforms to ANSI/TIA/EIA-644 LVDS standard  
For more details, please refer to the APPLICATION  
INFORMATION section of this datasheet.  
Connection Diagram  
Order Number DS90LV110TMTC  
PW0028A Package  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2001–2013, Texas Instruments Incorporated  
 

DS90LV110TMTC 替代型号

型号 品牌 替代类型 描述 数据表
DS90LV110TMTC/NOPB TI

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1:10 LVDS 数据/时钟分配器 | PW | 28 | -40 to 85
DS90LV110ATMT/NOPB TI

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具有失效防护的 1:10 LVDS 数据/时钟分配器 | PW | 28 | -40 to

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