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DS1022 PDF预览

DS1022

更新时间: 2024-09-19 14:58:19
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莱迪思 - LATTICE /
页数 文件大小 规格书
59页 4861K
描述
ispMACH 4000ZE Family Data Sheet

DS1022 数据手册

 浏览型号DS1022的Datasheet PDF文件第2页浏览型号DS1022的Datasheet PDF文件第3页浏览型号DS1022的Datasheet PDF文件第4页浏览型号DS1022的Datasheet PDF文件第5页浏览型号DS1022的Datasheet PDF文件第6页浏览型号DS1022的Datasheet PDF文件第7页 
®
ispMACH 4000ZE Family  
1.8 V In-System Programmable  
Ultra Low Power PLDs  
October 2015  
Data Sheet DS1022  
Broad Device Offering  
• 32 to 256 macrocells  
Features  
High Performance  
• Multiple temperature range support  
– Commercial: 0 to 90 °C junction (T )  
– Industrial: –40 to 105 °C junction (T )  
Space-saving ucBGA and csBGA packages*  
• f  
= 260 MHz maximum operating frequency  
MAX  
j
• t = 4.4 ns propagation delay  
PD  
j
• Up to four global clock pins with programmable  
clock polarity control  
• Up to 80 PTs per output  
Easy System Integration  
• Operation with 3.3V, 2.5V, 1.8V or 1.5V  
LVCMOS I/O  
Ease of Design  
• Flexible CPLD macrocells with individual clock,  
reset, preset and clock enable controls  
• Up to four global OE controls  
• 5 V tolerant I/O for LVCMOS 3.3, LVTTL, and  
PCI interfaces  
• Hot-socketing support  
• Open-drain output option  
• Programmable output slew rate  
• 3.3V PCI compatible  
• Individual local OE control per I/O pin  
• Excellent First-Time-FitTM and refit  
• Wide input gating (36 input logic blocks) for fast  
counters, state machines and address decoders  
• I/O pins with fast setup path  
Input hysteresis*  
• 1.8V core power supply  
• IEEE 1149.1 boundary scan testable  
• IEEE 1532 ISC compliant  
Ultra Low Power  
• Standby current as low as 10 µA typical  
• 1.8V core; low dynamic power  
• Operational down to 1.6 V V  
CC  
• 1.8 V In-System Programmable (ISP™) using  
Boundary Scan Test Access Port (TAP)  
• Pb-free package options (only)  
On-chip user oscillator and timer*  
• Superior solution for power sensitive consumer  
applications  
• Per pin pull-up, pull-down or bus keeper  
control*  
Power Guard with multiple enable signals*  
*New enhanced features over original ispMACH 4000Z  
Table 1. ispMACH 4000ZE Family Selection Guide  
ispMACH 4032ZE  
ispMACH 4064ZE  
ispMACH 4128ZE  
ispMACH 4256ZE  
Macrocells  
PD (ns)  
32  
4.4  
64  
4.7  
128  
5.8  
256  
5.8  
t
tS (ns)  
2.2  
2.5  
2.9  
2.9  
tCO (ns)  
3.0  
3.2  
3.8  
3.8  
f
MAX (MHz)  
260  
1.8 V  
241  
1.8 V  
200  
1.8 V  
200  
1.8 V  
Supply Voltages (V)  
Packages1 (I/O + Dedicated Inputs)  
48-Pin TQFP (7 mm x 7mm)  
64-Ball csBGA (5 mm x 5mm)  
64-Ball ucBGA (4 mm x 4mm)  
100-Pin TQFP (14 mm x 14mm)  
132-Ball ucBGA (6 mm x 6mm)  
144-Pin TQFP (20 mm x 20mm)  
144-Ball csBGA (7 mm x 7mm)  
1. Pb-free only.  
32+4  
32+4  
32+4  
48+4  
48+4  
64+10  
64+10  
96+4  
96+4  
96+4  
64+10  
96+14  
108+4  
64+10  
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand  
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.  
www.latticesemi.com  
1
DS1022_1.9  

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