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DS1023-50 PDF预览

DS1023-50

更新时间: 2024-09-18 20:01:19
品牌 Logo 应用领域
达拉斯 - DALLAS 光电二极管延迟线
页数 文件大小 规格书
16页 238K
描述
Delay Line, Programmable, 1-Func, 1-Tap, CMOS, PDIP16,

DS1023-50 技术参数

是否Rohs认证: 不符合生命周期:Transferred
Reach Compliance Code:unknown风险等级:5.67
JESD-30 代码:R-PDIP-T16JESD-609代码:e0
功能数量:1抽头/阶步数:1
端子数量:16最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:5 V最大电源电流(ICC):60 mA
可编程延迟线:YESProp。Delay @ Nom-Sup:144 ns
认证状态:Not Qualified子类别:Delay Lines
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

DS1023-50 数据手册

 浏览型号DS1023-50的Datasheet PDF文件第2页浏览型号DS1023-50的Datasheet PDF文件第3页浏览型号DS1023-50的Datasheet PDF文件第4页浏览型号DS1023-50的Datasheet PDF文件第5页浏览型号DS1023-50的Datasheet PDF文件第6页浏览型号DS1023-50的Datasheet PDF文件第7页 
DS1023  
8-Bit Programmable Timing Element  
www.maxim-ic.com  
FEATURES  
PIN ASSIGNMENT  
C Step sizes of 0.25 ns, 0.5 ns, 1 ns, 2 ns, 5 ns  
C On-chip reference delay  
VCC  
IN  
LE  
1
16  
15  
14  
13  
12  
C Configurable as delay line, pulse width  
OUT/OUT  
P/S  
2
3
modulator, or free-running oscillator  
Q/P0  
CLK/P1  
D/P2  
P3  
C Can delay clocks by a full period or more  
C Guaranteed monotonicity  
C Parallel or serial programming  
C Single 5V supply  
P7  
P6  
MS  
4
5
6
11  
P4  
10  
9
P5  
REF/PWM  
7
8
GND  
C 16-pin DIP or SOIC package  
DS1023 300-mil DIP  
DS1023S 300-mil SOIC  
PIN DESCRIPTION  
IN  
- Input  
P0/Q  
- Parallel Input P0 (parallel mode)  
- Serial Data Output (serial mode)  
- Parallel Input P1 (parallel mode)  
- Serial Input Clock (serial mode)  
- Parallel Input P2 (parallel mode)  
- Serial Data Input (serial mode)  
- Remaining Parallel Inputs  
- Ground  
P1/CLK  
P2/D  
P3 - P7  
GND  
OUT/OUT  
- Output  
REF/PWM - Reference or PWM Output  
P /S  
- Parallel / Serial Programming  
Select  
MS  
LE  
- Output Mode Select  
- Input Latch Enable  
- Supply Voltage  
VCC  
DESCRIPTION  
The DS1023 is an 8-bit programmable delay line similar in function to the DS1020/DS1021.  
Additional features have been added to extend the range of applications:  
The internal delay line architecture has been revised to allow clock signals to be delayed by up to a full  
period or more. Combined with an on-chip reference delay (to offset the inherent or “step zero” delay of  
the device) clock phase can now be varied over the full 0-360 degree range.  
1 of 16  
101001  

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