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DS1023-200 PDF预览

DS1023-200

更新时间: 2024-09-17 22:34:07
品牌 Logo 应用领域
达拉斯 - DALLAS 延迟线逻辑集成电路光电二极管
页数 文件大小 规格书
16页 263K
描述
8-Bit Programmable Timing Element

DS1023-200 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:0.300 INCH, DIP-16Reach Compliance Code:unknown
风险等级:5.71系列:CMOS/TTL
输入频率最大值(fmax):25 MHzJESD-30 代码:R-PDIP-T16
JESD-609代码:e0逻辑集成电路类型:SILICON DELAY LINE
功能数量:1抽头/阶步数:255
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5 V
最大电源电流(ICC):60 mA可编程延迟线:YES
Prop。Delay @ Nom-Sup:527 ns认证状态:Not Qualified
子类别:Delay Lines最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL总延迟标称(td):524 ns
Base Number Matches:1

DS1023-200 数据手册

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DS1023  
8-Bit Programmable Timing Element  
www.dalsemi.com  
FEATURES  
PIN ASSIGNMENT  
Step sizes of 0.25 ns, 0.5 ns, 1 ns, 2 ns, 5 ns  
On-chip reference delay  
VCC  
IN  
LE  
1
16  
15  
14  
13  
12  
Configurable as delay line, pulse width  
OUT/OUT  
P/S  
2
3
modulator, or free-running oscillator  
Q/P0  
CLK/P1  
D/P2  
P3  
Can delay clocks by a full period or more  
Guaranteed monotonicity  
P7  
P6  
MS  
4
5
6
11  
Parallel or serial programming  
Single 5V supply  
P4  
10  
9
P5  
7
8
REF/PWM  
GND  
16-pin DIP or SOIC package  
DS1023 300-mil DIP  
DS1023S 300-mil SOIC  
PIN DESCRIPTION  
IN  
- Input  
P0/Q  
- Parallel Input P0 (parallel mode)  
- Serial Data Output (serial mode)  
- Parallel Input P1 (parallel mode)  
- Serial Input Clock (serial mode)  
- Parallel Input P2 (parallel mode)  
- Serial Data Input (serial mode)  
- Remaining Parallel Inputs  
- Ground  
P1/CLK  
P2/D  
P3 - P7  
GND  
OUT/OUT  
- Output  
REF/PWM - Reference or PWM Output  
P /S  
- Parallel / Serial Programming  
Select  
MS  
LE  
VCC  
- Output Mode Select  
- Input Latch Enable  
- Supply Voltage  
DESCRIPTION  
The DS1023 is an 8-bit programmable delay line similar in function to the DS1020/DS1021.  
Additional features have been added to extend the range of applications:  
The internal delay line architecture has been revised to allow clock signals to be delayed by up to a full  
period or more. Combined with an on-chip reference delay (to offset the inherent or “step zero” delay of  
the device) clock phase can now be varied over the full 0-360 degree range.  
1 of 16  
022300  

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