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DM74LS374CW PDF预览

DM74LS374CW

更新时间： 2024-11-01 21:18:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动逻辑集成电路
页数 文件大小 规格书
8页 88K
描述
Bus Driver, LS Series, 1-Func, 8-Bit, True Output, TTL, WAFER

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DM74LS374CW 技术参数

生命周期：Obsolete零件包装代码：WAFER
包装说明：DIE,Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.68
系列：LSJESD-30 代码：X-XUUC-N20
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
输出极性：TRUE封装主体材料：UNSPECIFIED
封装代码：DIE封装形状：UNSPECIFIED
封装形式：UNCASED CHIP传播延迟（tpd）：38 ns
认证状态：Not Qualified最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：TTL
温度等级：COMMERCIAL端子形式：NO LEAD
端子位置：UPPERBase Number Matches：1

DM74LS374CW 数据手册

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April 1986  
Revised March 2000  
DM74LS373 • DM74LS374  
3-STATE Octal D-Type Transparent Latches  
and Edge-Triggered Flip-Flops  
General Description  
Features  
■ Choice of 8 latches or 8 D-type flip-flops in a single  
These 8-bit registers feature totem-pole 3-STATE outputs  
designed specifically for driving highly-capacitive or rela-  
tively low-impedance loads. The high-impedance state and  
increased high-logic level drive provide these registers with  
the capability of being connected directly to and driving the  
bus lines in a bus-organized system without need for inter-  
face or pull-up components. They are particularly attractive  
for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
package  
■ 3-STATE bus-driving outputs  
■ Full parallel-access for loading  
■ Buffered control inputs  
■ P-N-P inputs reduce D-C loading on data lines  
The eight latches of the DM74LS373 are transparent D-  
type latches meaning that while the enable (G) is HIGH the  
Q outputs will follow the data (D) inputs. When the enable  
is taken LOW the output will be latched at the level of the  
data that was set up.  
The eight flip-flops of the DM74LS374 are edge-triggered  
D-type flip flops. On the positive transition of the clock, the  
Q outputs will be set to the logic states that were set up at  
the D inputs.  
A buffered output control input can be used to place the  
eight outputs in either a normal logic state (HIGH or LOW  
logic levels) or a high-impedance state. In the high-imped-  
ance state the outputs neither load nor drive the bus lines  
significantly.  
The output control does not affect the internal operation of  
the latches or flip-flops. That is, the old data can be  
retained or new data can be entered even while the outputs  
are OFF.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS373WM  
DM74LS373SJ  
DM74LS373N  
DM74LS374WM  
DM74LS374SJ  
IDM29901NC  
M20B  
M20D  
N20A  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2000 Fairchild Semiconductor Corporation  
DS006431  
www.fairchildsemi.com  
12345678

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与DM74LS374CW相关器件

型号 品牌 获取价格 描述 数据表
DM74LS374J NSC

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 		IC,FLIP-FLOP,OCTAL,D TYPE,LS-TTL,DIP,20PIN,CERAMIC
DM74LS374J/A+ ETC

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 		Octal D-Type Flip-Flop
DM74LS374N NSC

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 		TRI-STATEE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
DM74LS374N/A+ ETC

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 		Octal D-Type Flip-Flop
DM74LS374N/B+ ETC

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 		Octal D-Type Flip-Flop
DM74LS374SJ FAIRCHILD

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 		3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
DM74LS374SJX ETC

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 		Octal D-Type Flip-Flop
DM74LS374WM NSC

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 		TRI-STATEE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
DM74LS374WM FAIRCHILD

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 		3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
DM74LS374WMX FAIRCHILD

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 		Bus Driver, LS Series, 1-Func, 8-Bit, True Output, TTL, PDSO20, 0.300 INCH, MS-013, SOIC-2

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