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DM74LS375 PDF预览

DM74LS375

更新时间: 2024-01-12 19:56:49
品牌 Logo 应用领域
美国国家半导体 - NSC 锁存器
页数 文件大小 规格书
6页 106K
描述
4-Bit Latch

DM74LS375 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.24
系列:LSJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.305 mm
负载电容(CL):15 pF逻辑集成电路类型:D LATCH
最大I(ol):0.008 A位数:2
功能数量:2端子数量:16
最高工作温度:70 °C最低工作温度:
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:5 V最大电源电流(ICC):12 mA
Prop。Delay @ Nom-Sup:27 ns传播延迟(tpd):25 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:FF/Latches最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL触发器类型:HIGH LEVEL
宽度:7.62 mmBase Number Matches:1

DM74LS375 数据手册

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February 1992  
DM74LS375  
4-Bit Latch  
General Description  
The ’LS375 is a 4-bit D-type latch for use as temporary stor-  
age for binary information between processing units and in-  
put/output or indicator units. When its Enable (E) input is  
HIGH, a latch is transparent, i.e., the Q output will follow the  
D input each time it changes. When E is LOW a latch stores  
the last valid data present on the D input preceding the  
HIGH-to-LOW transition of E. The ’LS375 is functionally  
identical to the ’LS75 except for the corner power pins.  
Connection Diagram  
Logic Symbol  
Dual-In-Line Package  
TL/F/9830–2  
e
e
V
Pin 16  
CC  
GND  
Pin 8  
TL/F/9830–1  
Order Number DM74LS375M or DM74LS375N  
See NS Package Number M16A or N16E  
Pin Name  
Description  
Data Inputs  
D1D4  
E1, 2  
Latches 1, 2 Enable Inputs  
Latches 3, 4 Enable Inputs  
Latch Outputs  
E3, 4  
Q1Q4  
Q1Q4  
Complementary Latch Outputs  
C
1995 National Semiconductor Corporation  
TL/F/9830  
RRD-B30M115/Printed in U. S. A.  

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