Datasheet > DM74LS377N

DM74LS377N

更新时间： 2024-11-24 23:00:43

品牌	Logo	应用领域
美国国家半导体 - NSC		触发器逻辑集成电路光电二极管时钟
页数	文件大小	规格书
6页	146K
描述
Octal D Flip-Flop with Common Enable and Clock

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DM74LS377N 数据手册

May 1992

DM54LS377/DM74LS377

Octal D Flip-Flop with Common Enable and Clock

General Description

Features

8-bit high speed parallel registers

The ’LS377 is an 8-bit register built using advanced low

power Schottky technology. This register consists of eight

D-type flip-flops with a buffered common clock and a buff-

ered common input enable. The device is packaged in the

space-saving (0.3 inch row spacing) 20-pin package.

Positive edge-triggered D-type flip-flops

Fully buffered common clock and enable inputs

Connection Diagram

Dual-In-Line Package

TL/F/9831–1

Order Number DM54LS377E, DM54LS377J,

DM54LS377W, DM74LS377WM or DM74LS377N

See NS Package Number

E20A, J20A, M20B, N20A or W20A

Pin Names

Description

Enable Input (Active LOW)

Data Inputs

D0–D7

Clock Pulse Input (Active Rising Edge)

Flip-Flop Outputs

Q0–Q7

1995 National Semiconductor Corporation

TL/F/9831

RRD-B30M115/Printed in U. S. A.

12 3 4 5 6

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型号	品牌	获取价格	描述	数据表
DM74LS377WM	NSC	获取价格	Octal D Flip-Flop with Common Enable and Clock
DM74LS377WM	FAIRCHILD	获取价格	Octal D-Type Flip-Flop with Common Enable and Clock
DM74LS377WMX	FAIRCHILD	获取价格	Octal D-Type Flip-Flop
DM74LS378N	ROCHESTER	获取价格	D Flip-Flop, LS Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, TTL, PDIP16,
DM74LS379	NSC	获取价格	Quad Parallel Register with Enable
DM74LS379M	NSC	获取价格	Quad Parallel Register with Enable
DM74LS379M	ROCHESTER	获取价格	D Flip-Flop, LS Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, TTL,
DM74LS379MX	TI	获取价格	LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, 0.150 INCH,
DM74LS379N	NSC	获取价格	Quad Parallel Register with Enable
DM74LS379N	ROCHESTER	获取价格	D Flip-Flop, LS Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, TTL,