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DM74LS380AN PDF预览

DM74LS380AN

更新时间: 2024-11-27 20:28:11
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
6页 140K
描述
LS SERIES, 8-BIT DRIVER, CONFIGURABLE OUTPUT, PDIP24, PLASTIC, DIP-24

DM74LS380AN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP,Reach Compliance Code:unknown
风险等级:5.92其他特性:WITH SYNCHRONOUS CLEAR AND PRESET; WITH HOLD MODE; CLEAR OVERRIDES PRESET; PRESET OVERRIDES LOAD
系列:LSJESD-30 代码:R-PDIP-T24
JESD-609代码:e0长度:31.915 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
位数:8功能数量:1
端口数量:2端子数量:24
最高工作温度:75 °C最低工作温度:
输出特性:3-STATE输出极性:CONFIGURABLE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED最大电源电流(ICC):180 mA
传播延迟(tpd):15 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL EXTENDED端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

DM74LS380AN 数据手册

 浏览型号DM74LS380AN的Datasheet PDF文件第2页浏览型号DM74LS380AN的Datasheet PDF文件第3页浏览型号DM74LS380AN的Datasheet PDF文件第4页浏览型号DM74LS380AN的Datasheet PDF文件第5页浏览型号DM74LS380AN的Datasheet PDF文件第6页 
July 1989  
DM54LS380A/DM74LS380A  
Multifunction Octal Register  
General Description  
The ’LS380A is an 8-bit synchronous register with parallel  
load, load complement, preset, clear and hold capacity.  
Four control inputs (LD, POL, CLR, PR) provide one of four  
operations which occur synchronously on the rising edge of  
the clock (CK). The ’LS380A combines the features of the  
’LS374, ’LS377, ’LS273 and ’LS534 into a single 300 mil  
wide package.  
The output register (Q7Q0) is enabled when OE is LOW  
and disabled (HIZ) when OE is HIGH. The output drivers  
will sink 24 mA required for many bus interface standards.  
Features  
Y
Octal Register for general purpose interfacing applica-  
tions  
The LOAD operation loads the inputs (D7D0) into the out-  
put register (Q7Q0), when POL is HIGH, or loads the com-  
pliment of the inputs when POL is LOW. The CLEAR opera-  
tion resets the output register to all LOWs. The PRESET  
operation presets the output register to all HIGHs. The  
HOLD operation holds the previous value regardless of  
clock transitions. CLEAR overrides PRESET, PRESET over-  
rides LOAD, and LOAD overrides HOLD.  
Y
8 bits match byte boundaries  
Y
Low current PNP inputs reduce loading  
Y
Bus-structured pinout  
Y
TRI-STATE outputs  
É
24-pin SKINNYDIP saves space  
Y
Connection Diagram  
Top View  
TL/L/10229–1  
Order Number DM54LS380AJ, DM74LS380AJ, DM74LS380AN or DM74LS380AV  
See NS Package Number J24F, N24C or V28A  
Function Table  
OC CLK CLR PR LD POL D7D0 Q7Q0 Operation  
H
L
L
L
L
L
X
X
L
X
X
L
X
X
X
H
L
X
X
X
X
H
L
X
X
X
X
D
D
Z
L
HI–Z  
CLEAR  
u
u
u
u
u
H
H
H
H
H
Q
D
D
PRESET  
HOLD  
H
H
H
LOAD true  
LOAD comp  
L
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/L/10229  
RRD-B30M115/Printed in U. S. A.  

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