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DM74LS377 PDF预览

DM74LS377

更新时间: 2024-11-26 23:00:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器时钟
页数 文件大小 规格书
5页 58K
描述
Octal D-Type Flip-Flop with Common Enable and Clock

DM74LS377 数据手册

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October 1988  
Revised March 2000  
DM74LS377  
Octal D-Type Flip-Flop with Common Enable and Clock  
General Description  
Features  
The DM74LS377 is an 8-bit register built using advanced  
low power Schottky technology. This register consists of  
eight D-type flip-flops with a buffered common clock and a  
buffered common input enable. The device is packaged in  
the space-saving (0.3 inch row spacing) 20-pin package.  
8-bit high speed parallel registers  
Positive edge-triggered D-type flip-flops  
Fully buffered common clock and enable inputs  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS377WM  
DM74LS377N  
M20B  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
V
= Pin 20  
CC  
GND = Pin 10  
Pin Descriptions  
Truth Table  
Pin Names  
Description  
Inputs  
Output  
Qn  
E
Enable Input (Active LOW)  
Data Inputs  
Dn  
E
H
L
CP  
D0–D7  
CP  
X
X
H
L
No Change  
Clock Pulse Input (Active Rising Edge)  
Flip-Flop Outputs  
H
L
Q0–Q7  
L
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
© 2000 Fairchild Semiconductor Corporation  
DS009831  
www.fairchildsemi.com  

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