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DAC5674 PDF预览

DAC5674

更新时间: 2024-11-28 22:40:31
品牌 Logo 应用领域
德州仪器 - TI 转换器数模转换器
页数 文件大小 规格书
32页 504K
描述
14BIT 400 MSPS, 2 X/ 4X INTERPOLATING COMMS DAC DIGITAL TO ANALOG CONVERTER

DAC5674 数据手册

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www.ti.com  
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ  
SLWS148 − SEPTEMBER 2003  
8
D
Differential Scalable Current Outputs: 2 mA to  
20 mA  
FEATURES  
D
D
D
200-MSPS Maximum Input Data Rate  
400-MSPS Maximum Update Rate DAC  
D
On-Chip 1.2-V Reference  
D
1.8-V Digital and 3.3-V Analog Supply  
Operation  
76-dBc SFDR Over Full First Nyquist Zone  
With Single Tone Input Signal (F = 21 MHz)  
D
D
D
1.8/3.3-V CMOS Compatible Interface  
Power Dissipation: 435 mW at 400 MSPS  
Package: 48-Pin TQFP  
out  
D
D
D
74-dBc ACPR W-CDMA at 15.36 MHz IF  
69-dBc ACPR W-CDMA at 30.72 MHz IF  
Selectable 2x or 4x Interpolation Filter  
− Linear Phase  
− 0.05-dB Passband Ripple  
− 80-dB Stopband Attenuation  
APPLICATIONS  
D
Cellular Base Transceiver Station Transmit  
Channel  
− CDMA: W−CDMA, CDMA2000, IS−95  
− TDMA: GSM, IS−136, EDGE/UWC−136  
− Stopband Transition 0.4−0.6 F  
data  
− nterpolation Filters Configurable in Either  
Low-Pass or High-Pass Mode, Allows For  
Selection Higher Order Image  
D
Test and Measurement: Arbitrary Waveform  
Generation  
D
D
Direct Digital Synthesis (DDS)  
D
On-chip 2x/4x PLL Clock Multiplier, PLL  
Bypass Mode  
Cable Modem Termination System  
DESCRIPTION  
The DAC5674 is a 14-bit resolution high-speed digital-to-analog converter (DAC) with integrated  
4x-interpolation filter, on-board clock multiplier, and on-chip voltage reference. The device has been designed  
for high-speed digital data transmission in wired and wireless communication systems, high-frequency  
direct-digital synthesis (DDS) and waveform reconstruction in test and measurement applications.  
The 4x-interpolation filter is implemented as a cascade of two 2x-interpolation filters, each of which can be  
configured for either low-pass or high-pass response. This enables the user to select one of the higher order  
images present at multiples of the input data rate clock while maintaining a low date input rate. The resulting  
high IF output frequency allows the user to omit the conventional first mixer in heterodyne transmitter  
architectures and directly up-convert to RF using only one mixer, thereby reducing system complexity and  
costs.  
In 4x-interpolation low-pass response mode, the DACs excellent spurious free dynamic range (SFDR) at  
intermediate frequencies located in the first Nyquist zone (up to 40 MHz) allows for multicarrier transmission  
in cellular base transceiver stations (BTS). The low-pass interpolation mode thereby relaxes image filter  
requirements by filtering out the images in the adjacent Nyquist zones.  
The DAC5674 PLL clock multiplier controls all internal clocks for the digital filters and DAC core. The differential  
clock input and internal clock circuitry provides for optimum jitter performance. Sine wave clock input signal is  
supported. The PLL can be bypassed by an external clock running at the DAC core update rate. The clock  
divider of the PLL ensures that the digital filters operate at the correct clock frequencies.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments  
semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢐꢖ ꢗ ꢀꢞ ꢂ ꢋꢊ ꢗꢔ ꢀ ꢁꢋꢁ ꢟꢠ ꢡꢚ ꢢ ꢛꢣ ꢤꢟꢚꢠ ꢟꢜ ꢥꢦ ꢢ ꢢ ꢧꢠꢤ ꢣꢜ ꢚꢡ ꢨꢦꢩ ꢪꢟꢥ ꢣꢤꢟ ꢚꢠ ꢫꢣ ꢤꢧꢬ ꢐꢢ ꢚꢫꢦ ꢥꢤꢜ  
ꢥ ꢚꢠ ꢡꢚꢢ ꢛ ꢤꢚ ꢜ ꢨꢧ ꢥ ꢟ ꢡꢟ ꢥ ꢣ ꢤꢟ ꢚꢠꢜ ꢨ ꢧꢢ ꢤꢭꢧ ꢤꢧ ꢢ ꢛꢜ ꢚꢡ ꢋꢧꢒ ꢣꢜ ꢊꢠꢜ ꢤꢢ ꢦꢛ ꢧꢠꢤ ꢜ ꢜꢤ ꢣꢠꢫ ꢣꢢ ꢫ ꢮ ꢣꢢ ꢢ ꢣ ꢠꢤꢯꢬ  
ꢐꢢ ꢚ ꢫꢦꢥ ꢤ ꢟꢚ ꢠ ꢨꢢ ꢚ ꢥ ꢧ ꢜ ꢜ ꢟꢠ ꢰ ꢫꢚ ꢧ ꢜ ꢠꢚꢤ ꢠꢧ ꢥꢧ ꢜꢜ ꢣꢢ ꢟꢪ ꢯ ꢟꢠꢥ ꢪꢦꢫ ꢧ ꢤꢧ ꢜꢤꢟ ꢠꢰ ꢚꢡ ꢣꢪ ꢪ ꢨꢣ ꢢ ꢣꢛ ꢧꢤꢧ ꢢ ꢜꢬ  
Copyright 2003, Texas Instruments Incorporated  

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