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DAC5670MGEM/EM PDF预览

DAC5670MGEM/EM

更新时间: 2024-11-30 01:16:55
品牌 Logo 应用领域
德州仪器 - TI 转换器
页数 文件大小 规格书
34页 813K
描述
DAC5670-SP 14-Bit 2.4-GSPS Digital-to-Analog Converter (DAC)

DAC5670MGEM/EM 技术参数

生命周期:Active零件包装代码:BGA
包装说明:BGA,针数:192
Reach Compliance Code:not_compliant风险等级:5.79
最大模拟输出电压:4.1 V最小模拟输出电压:2.5 V
转换器类型:D/A CONVERTER输入位码:BINARY
JESD-30 代码:S-CBGA-B192JESD-609代码:e0
长度:19 mm最大线性误差 (EL):0.0458%
位数:14功能数量:1
端子数量:192最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):NOT SPECIFIED
采样速率:2400 MHz座面最大高度:3.3 mm
标称安定时间 (tstl):0.0035 µs标称供电电压:3.3 V
表面贴装:YES温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:19 mm
Base Number Matches:1

DAC5670MGEM/EM 数据手册

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DAC5670-SP  
SGLS386F JANUARY 2009REVISED OCTOBER 2014  
DAC5670-SP 14-Bit 2.4-GSPS Digital-to-Analog Converter (DAC)  
1 Features  
3 Description  
The DAC5670 is a 14-bit 2.4-GSPS DAC with dual  
1
14-Bit Resolution  
demultiplexed differential input ports. The DAC5670  
is clocked at the DAC sample rate and the two input  
ports run at a maximum of 1.2 GSPS. An additional  
reference bit input sequence is used to adjust the  
output clock delay to the data source, optimizing the  
internal data latching clock relative to this reference  
bit with a delay lock loop (DLL). Alternatively, the DLL  
may be bypassed and the timing interface managed  
by controlling DATA setup and hold timing to  
DLYCLK.  
2.4-GSPS Max Update Rate DAC  
Dual Differential Input Ports  
Even/Odd Demultiplexed Data  
Maximum 1.2 GSPS Each Port, 2.4 GSPS  
Total  
Dual 14-Bit Inputs + 1 Reference Bit  
DDR Output Clock  
DLL Optimized Clock Timing Synchronized to  
Reference Bit  
The DAC5670 can also accept data up to 1.2 GSPS  
using only the A input port. In the single port modes,  
options include: repeating the input sample (A_ONLY  
mode), 2× interpolation by zero stuff (A_ONLY_ZS  
mode), or 2× interpolation by repeating and inverting  
the input sample (A_ONLY_INV). These modes are  
used to double the input sample rate up to 2.4 GSPS.  
LVDS and HyperTransport™ Voltage Level  
Compatible  
Internal 100-Terminations for Data and  
Reference Bit Inputs  
Selectable 2× Interpolation With Fs / 2 Mixing  
Differential Scalable Current Outputs: 5 to 30 mA  
On-Chip 1.2-V Reference  
The DAC5670 operates with a single 3- to 3.6-V  
supply voltage. Power dissipation is 2 W at maximum  
operating conditions. The DAC5670 provides  
nominal full-scale differential current-output of 20 mA,  
supporting both single-ended and differential  
applications. An on-chip 1.2-V temperature-  
compensated bandgap reference and control  
amplifier allows the user to adjust the full-scale output  
current from the nominal 20 mA to as low as 5 mA or  
as high as 30 mA.  
a
3.3-V Analog Supply Operation  
Power Dissipation: 2 W  
192-Ball CBGA (GEM) Package  
QML-V Qualified, SMD 5962-07247  
Military Temperature Range (–55°C to 125°C  
Tcase  
)
Device Information(1)  
2 Applications  
PART NUMBER  
PACKAGE  
BODY SIZE (NOM)  
Test and Measurement: Arbitrary Waveform  
Generator  
DAC5670-SP  
CBGA (192)  
19.00 mm × 19.00 mm  
Communications  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
Engineering evaluation (/EM) samples are  
available  
Simplified Schematic  
(1)  
These units are intended for engineering evaluation only.  
They are processed to a non-compliant flow (that is, no burn-  
in, and so forth) and are tested to a temperature rating of  
25°C only. These units are not suitable for qualification,  
production, radiation testing, or flight use. Parts are not  
warranted for performance over the full MIL specified  
temperature range of –55°C to 125°C or operating life.  
SLEEP  
Mode Controls  
CSBIAS  
CSBIAS_IN  
DA_P[13:0]  
IOUT_P  
DA_N[13:0]  
DB_P[13:0]  
14 bit  
2.4Gsps  
DAC  
Input  
Registers  
Demux  
and  
Format  
IOUT_N  
DB_N[13:0]  
DTCLK_P  
RBIASOUT  
RBIASIN  
Phase  
Detector  
Loop  
Filter  
REFIO_IN  
REFIO  
DTCLK_N  
Bandgap  
Ref  
LOCK  
RESTART  
÷2  
÷2  
INV_CLK  
DLYCLK_P  
DLYCLK_N  
Variable  
Delay  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 
 

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