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CY7C9536B-BLI PDF预览

CY7C9536B-BLI

更新时间: 2024-02-27 19:01:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
页数 文件大小 规格书
46页 761K
描述
OC-48/STM-16 Framer with VC - POSIC2GVC⑩

CY7C9536B-BLI 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:LBGA,针数:50
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
应用程序:ATM;SDH;SONETJESD-30 代码:S-XBGA-B50
长度:37.5 mm功能数量:1
端子数量:50最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:LBGA封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE认证状态:Not Qualified
座面最大高度:1.57 mm标称供电电压:1.8 V
表面贴装:YES技术:CMOS
电信集成电路类型:ATM/SONET/SDH TRANSCEIVER温度等级:INDUSTRIAL
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM宽度:37.5 mm
Base Number Matches:1

CY7C9536B-BLI 数据手册

 浏览型号CY7C9536B-BLI的Datasheet PDF文件第4页浏览型号CY7C9536B-BLI的Datasheet PDF文件第5页浏览型号CY7C9536B-BLI的Datasheet PDF文件第6页浏览型号CY7C9536B-BLI的Datasheet PDF文件第8页浏览型号CY7C9536B-BLI的Datasheet PDF文件第9页浏览型号CY7C9536B-BLI的Datasheet PDF文件第10页 
CONFIDENTIAL  
CY7C9536B  
System Memory at  
Host System  
Tagging enables sorting of packets by  
Host System  
Tag #0  
Control Packets  
Data  
Tag #1  
POSIC  
Data  
Packets  
Data  
Tag #2  
Packets not  
belonging to this  
Node  
SONET/SDH  
Data  
Tag #n  
Data  
........  
TTL-expired and  
other discard  
packets  
Tag #13  
Data  
Errored packets  
(CRC and Parity)  
Tag #14  
Data  
Node-sourced  
packets to be  
sinked  
Tag #15  
Data  
Figure 4. Frame Tagging Engine Data Sorting Diagram  
Table 2. Configuration Options  
CPU Interface  
Bus Width  
8 bits  
Clock Frequency  
19.44 MHz  
Line Rate  
OC-3/STM-1  
POSIC2GVC can interface with 16-bit or 32-bit CPU. The CPU  
interface can be pin configured to be compatible with Motorola  
or Intel bus interface. The CPU interface provides access to  
all registers of POSIC2GVC, collates all interrupt generated by  
various blocks and also supports control packet transfers.  
8 bits  
77.76 MHz  
OC-12/STM-4  
OC-12/STM-4  
OC-48/STM-16  
OC-48/STM-16  
16 bits  
16 bits  
32 bits  
38.88 MHz  
155.52 MHz  
77.76 MHz  
Line Interface  
The line interface/fiber side interface is configurable as 8 bit,  
16-bit or 32-bit depending on the clock frequency and data  
rate. The options shown in Table 2 are available.  
Clock Source  
The transmit clock can be programmed to be one of the  
following sources:  
• Received clock supplied by the PHY  
• External transmit clock source.  
Document #: 38-02078 Rev. *G  
Page 7 of 46  

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