Datasheet > CY7C25422KV18-333BZXC

CY7C25422KV18-333BZXC

更新时间： 2024-02-20 23:38:10

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
28页	569K
描述
QDR SRAM, 4MX18, CMOS, PBGA165, FBGA-165

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CY7C25422KV18-333BZXC 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	LBGA,	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
Factory Lead Time：	1 week	风险等级：	5.78
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PBGA-B165	长度：	15 mm
内存密度：	75497472 bit	内存集成电路类型：	QDR SRAM
内存宽度：	18	功能数量：	1
端子数量：	165	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	4MX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	座面最大高度：	1.4 mm
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	13 mm	Base Number Matches：	1

CY7C25422KV18-333BZXC 数据手册

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CY7C25422KV18

72-Mbit QDR II+ SRAM Two-Word

Burst Architecture (2.0 Cycle Read Latency)with ODT

72-Mbit QDR^®II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT

■ JTAG 1149.1 compatible test access port

Features

■ Phase Locked Loop (PLL) for accurate data placement

■ Separate independent read and write data ports

❐ Supports concurrent transactions

Configurations

■ 333 MHz clock for high bandwidth

With Read Cycle Latency of 2.0 cycles:

■ Two-word burst for reducing address bus frequency

CY7C25422KV18 – 4M × 18

■ DoubleDataRate(DDR)interfacesonbothreadandwriteports

(data transferred at 666 MHz) at 333 MHz

Functional Description

The CY7C25422KV18 are 1.8 V Synchronous Pipelined

SRAMs, equipped with QDR^®II+ architecture. Similar to QDR II

architecture, QDR II+ architecture consists of two separate ports:

the read port and the write port to access the memory array. The

read port has dedicated data outputs to support read operations

and the write port has dedicated data inputs to support write

operations. QDR II+ architecture has separate data inputs and

data outputs to completely eliminate the need to “turnaround” the

data bus that exists with common devices. Access to each port

is through a common address bus. Addresses for read and write

addresses are latched on alternate rising edges of the input (K)

clock. Accesses to the QDR II+ read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with two 18-bit

words (CY7C25422KV18) that burst sequentially into or out of

the device. Because data can be transferred into and out of the

device on every rising edge of both input clocks (K and K),

memory bandwidth is maximized while simplifying system

design by eliminating bus “turnarounds”.

■ Available in 2.0 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ On-Die Termination (ODT) feature

❐ Supported for D_[x:0], BWS_[x:0], and K/K inputs

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR^®II+ operates with 2.0 cycle read latency when DOFF is

asserted HIGH

■ OperatessimilartoQDRIdevicewith1cyclereadlatencywhen

DOFF is asserted LOW

These devices have an On-Die Termination feature supported

for D_[x:0], BWS_[x:0], and K/K inputs, which helps eliminate

external termination resistors, reduce cost, reduce board area,

and simplify board routing.

■ Available in × 18 configurations

■ Full data coherency, providing most current data

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

[1]

■ Core V_DD= 1.8 V± 0.1 V; V_DDQ= 1.4 V to V_DD

❐ Supports both 1.5 V and 1.8 V supply

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in Pb-free packages

For a complete list of related documentation, click here.

Selection Guide

Description

Maximum Operating Frequency

333 MHz Unit

333

810

MHz

Maximum Operating Current

× 18

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

= 1.4V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-90368 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 3, 2018

12 3 4 5 6 7...28

中文翻译

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与CY7C25422KV18-333BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C25422KV18-333BZXI	CYPRESS	获取价格	QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, FBGA-165
CY7C2542KV18	CYPRESS	获取价格	72-Mbit QDRÂ®II SRAM 2-Word Burst Architectur
CY7C25442KV18-300BZI	CYPRESS	获取价格	QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 MM X 13 MM, 1.4 MM HEIGHT, MO-216, FBGA-165
CY7C25442KV18-333BZI	CYPRESS	获取价格	QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 MM X 13 MM, 1.4 MM HEIGHT, MO-216, FBGA-165
CY7C25442KV18-333BZI	INFINEON	获取价格	Synchronous SRAM
CY7C25442KV18-333BZXI	CYPRESS	获取价格	QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, FBGA-165
CY7C25442KV18-333BZXI	INFINEON	获取价格	Synchronous SRAM
CY7C254-45DC	CYPRESS	获取价格	OTP ROM, 16KX8, 45ns, CMOS, CDIP28, 0.600 INCH, CERDIP-28
CY7C254-45DI	CYPRESS	获取价格	OTP ROM, 16KX8, 45ns, CMOS, CDIP28, 0.600 INCH, CERDIP-28
CY7C254-45DMB	CYPRESS	获取价格	OTP ROM, 16KX8, 45ns, CMOS, CDIP28, 0.600 INCH, CERDIP-28

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