Datasheet > 存储 > SRAM> CY7C2561KV18-400BZXC

CY7C2561KV18-400BZXC

更新时间： 2024-11-27 06:51:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
29页	824K
描述
72-Mbit QDR-II+ SRAM 4-Word Burst Architecture

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CY7C2561KV18-400BZXC 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	15 X 13 MM, 1.4 MM HEIGHT, LEAD FREE, FBGA-165
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.84	最长访问时间：	0.45 ns
其他特性：	PIPELINED ARCHITECTURE	JESD-30 代码：	R-PBGA-B165
长度：	15 mm	内存密度：	67108864 bit
内存集成电路类型：	QDR SRAM	内存宽度：	8
功能数量：	1	端子数量：	165
字数：	8388608 words	字数代码：	8000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	8MX8
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
宽度：	13 mm	Base Number Matches：	1

CY7C2561KV18-400BZXC 数据手册

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CY7C2561KV18, CY7C2576KV18

CY7C2563KV18, CY7C2565KV18

PRELIMINARY

72-Mbit QDR™-II+ SRAM 4-Word Burst

Architecture (2.5 Cycle Read Latency) with ODT

Features

Configurations

■ Separate independent read and write data ports

❐ Supports concurrent transactions

With Read Cycle Latency of 2.5 cycles:

CY7C2561KV18 – 8M x 8

■ 550 MHz clock for high bandwidth

CY7C2576KV18 – 8M x 9

CY7C2563KV18 – 4M x 18

CY7C2565KV18 – 2M x 36

■ 4-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces on both read and write

ports (data transferred at 1100 MHz) at 550 MHz

Functional Description

■ Available in 2.5 clock cycle latency

The CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and

CY7C2565KV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR-II+ architecture. Similar to QDR-II archi-

tecture, QDR-II+ architecture consists of two separate ports: the

read port and the write port to access the memory array. The

read port has dedicated data outputs to support read operations

and the write port has dedicated data inputs to support write

operations. QDR-II+ architecture has separate data inputs and

data outputs to completely eliminate the need to “turn-around”

the data bus that exists with common IO devices. Each port is

accessed through a common address bus. Addresses for read

and write addresses are latched on alternate rising edges of the

input (K) clock. Accesses to the QDR-II+ read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with four 8-bit

words (CY7C2561KV18), 9-bit words (CY7C2576KV18), 18-bit

words (CY7C2563KV18), or 36-bit words (CY7C2565KV18) that

burst sequentially into or out of the device. Because data is trans-

ferred into and out of the device on every rising edge of both input

clocks (K and K), memory bandwidth is maximized while simpli-

fying system design by eliminating bus “turn-arounds”.

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ On-Die Termination (ODT) feature

❐ Supported for D_[x:0], BWS_[x:0], and K/K inputs

■ Single multiplexed address input bus latches address inputs

for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR™-II+ operates with 2.5 cycle read latency when DOFF is

asserted HIGH

■ Operates similar to QDR-I device with 1 cycle read latency

when DOFF is asserted LOW

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency, providing most current data

These devices have an On-Die Termination feature supported

for D_[x:0], BWS_[x:0], and K/K inputs, which helps eliminate

external termination resistors, reduce cost, reduce board area,

and simplify board routing.

[1]

■ Core V_DD= 1.8V± 0.1V; IO V_DDQ= 1.4V to V_DD

❐ Supports both 1.5V and 1.8V IO supply

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ Phase Locked Loop (PLL) for accurate data placement

Table 1. Selection Guide

Description

Maximum Operating Frequency

Maximum Operating Current

550 MHz

500 MHz

500

450 MHz

450

400 MHz

400

Unit

MHz

550

900

920

830

760

690

830

760

690

x18

x36

850

780

710

1310

1210

1100

1000

Note

1. The Cypress QDR-II+ devices surpass the QDR consortium specification and can support V

= 1.4V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-15887 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 24, 2009

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与CY7C2561KV18-400BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C2561KV18-400BZXI	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2561KV18-450BZC	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2561KV18-450BZI	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2561KV18-450BZXC	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2561KV18-450BZXI	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2561KV18-500BZC	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2561KV18-500BZI	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2561KV18-500BZXC	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2561KV18-500BZXI	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2561KV18-550BZC	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture

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