Datasheet > CY7C25632KV18-500BZXI

CY7C25632KV18-500BZXI

更新时间： 2024-02-11 01:40:42

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	496K
描述
72-Mbit QDRÂ® II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

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CY7C25632KV18-500BZXI 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	LBGA, BGA165,11X15,40	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
Factory Lead Time：	1 week	风险等级：	2.3
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	500 MHz	I/O 类型：	SEPARATE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e1
长度：	15 mm	内存密度：	75497472 bit
内存集成电路类型：	QDR SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	4MX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大待机电流：	0.36 A	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	0.85 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	13 mm
Base Number Matches：	1

CY7C25632KV18-500BZXI 数据手册

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CY7C25632KV18

CY7C25652KV18

72-Mbit QDR^®II+ SRAM Four-Word Burst Architecture

(2.5 Cycle Read Latency) with ODT

72-Mbit QDR^®II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

■ JTAG 1149.1 compatible test access port

Features

■ Phase-locked loop (PLL) for accurate data placement

■ Separate independent read and write data ports

❐ Supports concurrent transactions

Configurations

■ 550 MHz clock for high bandwidth

With Read Cycle Latency of 2.5 cycles

CY7C25632KV18 – 4 M × 18

■ Four-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces on both read and write ports

(data transferred at 1100 MHz) at 550 MHz

CY7C25652KV18 – 2 M × 36

Functional Description

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

The CY7C25632KV18 and CY7C25652KV18 are 1.8 V

Synchronous Pipelined SRAMs, equipped with QDR II+

architecture. Similar to QDR II architecture, QDR II+ architecture

consists of two separate ports: the read port and the write port to

access the memory array. The read port has dedicated data

outputs to support read operations and the write port has

dedicated data inputs to support write operations. QDR II+

architecture has separate data inputs and data outputs to

completely eliminate the need to “turn-around” the data bus that

exists with common I/O devices. Each port is accessed through

a common address bus. Addresses for read and write addresses

are latched on alternate rising edges of the input (K) clock.

Accesses to the QDR II+ read and write ports are completely

independent of one another. To maximize data throughput, both

read and write ports are equipped with DDR interfaces. Each

address location is associated with four 18-bit words

(CY7C25632KV18), or 36-bit words (CY7C25652KV18) that

burst sequentially into or out of the device. Because data is

transferred into and out of the device on every rising edge of both

input clocks (K and K), memory bandwidth is maximized while

simplifying system design by eliminating bus “turn-arounds”.

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ On-die termination (ODT) feature

❐ Supported for D_[x:0], BWS_[x:0], and K/K inputs

■ Single multiplexed address input bus latches address inputs

for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR^®II+ operates with 2.5 cycle read latency when DOFF is

asserted HIGH

■ OperatessimilartoQDRIdevicewith1cyclereadlatencywhen

DOFF is asserted LOW

■ Available in × 18, and × 36 configurations

These devices have an On-Die Termination feature supported

for D_[x:0], BWS_[x:0], and K/K inputs, which helps eliminate

external termination resistors, reduce cost, reduce board area,

and simplify board routing.

■ Full data coherency, providing most current data

[1]

■ Core V_DD= 1.8 V ± 0.1 V; I/O V_DDQ= 1.4 V to V_DD

❐ Supports both 1.5 V and 1.8 V I/O supply

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Description

Maximum Operating Frequency

Maximum Operating Current

550 MHz

550

500 MHz

500

450 MHz

450

400 MHz Unit

400

710

MHz

× 18

× 36

920

850

780

1310

1210

1100

1000

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

= 1.4 V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-66482 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 21, 2012

12 3 4 5 6 7...31

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与CY7C25632KV18-500BZXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C25632KV18-550BZC	CYPRESS	获取价格	72-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C25632KV18-550BZC	INFINEON	获取价格	Synchronous SRAM
CY7C25632KV18-550BZXI	CYPRESS	获取价格	72-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C25632KV18-550BZXI	INFINEON	获取价格	Synchronous SRAM
CY7C2563KV18	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2563KV18-400BZC	ROCHESTER	获取价格	4MX18 QDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CY7C2563KV18-400BZC	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2563KV18-400BZI	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2563KV18-400BZXC	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C2563KV18-400BZXI	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture

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