CY7C2540KV18, CY7C2555KV18
CY7C2542KV18, CY7C2544KV18
72-Mbit QDR®II+ SRAM 2-Word Burst
Architecture (2.0 Cycle Read Latency) with ODT
Features
Configurations
■ Separate independent read and write data ports
❐ Supports concurrent transactions
With Read Cycle Latency of 2.0 cycles:
CY7C2540KV18 – 8M x 8
■ 333 MHz clock for high bandwidth
CY7C2555KV18 – 8M x 9
CY7C2542KV18 – 4M x 18
CY7C2544KV18 – 2M x 36
■ 2-word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces on both read and write
ports (data transferred at 666 MHz) at 333 MHz
Functional Description
■ Available in 2.0 clock cycle latency
The CY7C2540KV18, CY7C2555KV18, CY7C2542KV18, and
CY7C2544KV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR®-II+ architecture. Similar to QDR II archi-
tecture, QDR II+ architecture consists of two separate ports: the
read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus that exists with common IO devices. Access to each
port is through a common address bus. Addresses for read and
write addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the QDR II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with two 8-bit
words (CY7C2540KV18), 9-bit words (CY7C2555KV18), 18-bit
words (CY7C2542KV18), or 36-bit words (CY7C2544KV18) that
burst sequentially into or out of the device. Because data can be
transferred into and out of the device on every rising edge of both
input clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus “turn-arounds”.
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ On-Die Termination (ODT) feature
❐ Supported for D[x:0], BWS[x:0], and K/K inputs
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR®II+ operates with 2.0 cycle read latency when DOFF is
asserted HIGH
■ OperatessimilartoQDRIdevicewith1cyclereadlatencywhen
DOFF is asserted LOW
■ Available in x8, x9, x18, and x36 configurations
■ Full data coherency, providing most current data
These devices have an On-Die Termination feature supported
for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate
external termination resistors, reduce cost, reduce board area,
and simplify board routing.
[1]
■ Core VDD = 1.8V± 0.1V; IO VDDQ = 1.4V to VDD
❐ Supports both 1.5V and 1.8V IO supply
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
■ Phase Locked Loop (PLL) for accurate data placement
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
333 MHz
300 MHz
300
250 MHz
250
200 MHz
200
Unit
MHz
mA
333
790
790
810
990
x8
x9
730
640
540
730
640
540
x18
x36
750
650
550
910
790
660
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V
= 1.4V to V
.
DD
DDQ
Cypress Semiconductor Corporation
Document #: 001-15885 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 23, 2009
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