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CY7C1482V33-167BZC PDF预览

CY7C1482V33-167BZC

更新时间： 2024-09-17 22:22:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
30页 399K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

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中文翻译

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CY7C1482V33-167BZC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
针数：165Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.73最长访问时间：3.4 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：167 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B165
JESD-609代码：e0长度：17 mm
内存密度：75497472 bit内存集成电路类型：CACHE SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：165
字数：4194304 words字数代码：4000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：4MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：220
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.4 mm最小待机电流：3.14 V
子类别：SRAMs最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：15 mmBase Number Matches：1

CY7C1482V33-167BZC 数据手册

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CY7C1480V33  
CY7C1482V33  
CY7C1486V33  
PRELIMINARY  
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined  
Sync SRAM  
Features  
Functional Description[1]  
• Supports bus operation up to 250 MHz  
• Available speed grades are 250, 200,167 MHz  
• Registered inputs and outputs for pipelined operation  
• 3.3V core power supply  
The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM  
integrates 2,097,152 x 36/4,194,304 x 18,1,048,576 × 72  
SRAM cells with advanced synchronous peripheral circuitry  
and a two-bit counter for internal burst operation. All  
synchronous inputs are gated by registers controlled by a  
positive-edge-triggered Clock Input (CLK). The synchronous  
inputs include all addresses, all data inputs, address-pipelining  
Chip Enable (CE1), depth-expansion Chip Enables (CE2 and  
CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write  
Enables (BWX, and BWE), and Global Write (GW).  
Asynchronous inputs include the Output Enable (OE) and the  
ZZ pin.  
• 2.5V / 3.3V I/O operation  
• Fast clock-to-output times  
— 3.0 ns (for 250-MHz device)  
— 3.0 ns (for 200-MHz device)  
— 3.4 ns (for 167-MHz device)  
• Provide high-performance 3-1-1-1 access rate  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
• User-selectable burst counter supporting Intel®  
Pentium® interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to two or four bytes wide as  
controlled by the byte write control inputs. GW when active  
• Asynchronous output enable  
• Single Cycle Chip Deselect  
• CY7C1480V33 and CY7C1482V33 offered in  
JEDEC-standardlead-free100-pinTQFP, 165-BallfBGA  
packages. CY7C1486V33 available in 209-Ball BGA  
packages  
causes all bytes to be written.  
LOW  
The CY7C1480V33/CY7C1482V33/CY7C1486V33 operates  
from a +3.3V core power supply while all outputs may operate  
with either a +2.5 or +3.3V supply. All inputs and outputs are  
JEDEC-standard JESD8-5-compatible.  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• “ZZ” Sleep Mode Option  
Selection Guide  
250 MHz  
3.0  
200 MHz  
3.0  
167 MHz  
3.4  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
Shaded areas contain advance information.  
500  
500  
450  
mA  
mA  
120  
120  
120  
Please contact your local Cypress sales representative for availability of these parts.  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05283 Rev. *C  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised December 3, 2004  
1234567...30

中文翻译

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CY7C1482V33-167BZI CYPRESS

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CY7C1482V33-167BZXC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482V33-167BZXI CYPRESS

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CY7C1482V33-200AXC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482V33-200AXI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482V33-200BZI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482V33-200BZXC CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482V33-200BZXI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

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