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CY7C148-35PC PDF预览

CY7C148-35PC

更新时间: 2024-09-18 06:51:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 214K
描述
1Kx4 Static RAM

CY7C148-35PC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP18,.3
针数:18Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
Factory Lead Time:1 week风险等级:5.78
最长访问时间:35 ns其他特性:AUTOMATIC POWER-DOWN
I/O 类型:COMMONJESD-30 代码:R-PDIP-T18
JESD-609代码:e0长度:22.733 mm
内存密度:4096 bit内存集成电路类型:STANDARD SRAM
内存宽度:4湿度敏感等级:1
功能数量:1端口数量:1
端子数量:18字数:1024 words
字数代码:1000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:1KX4输出特性:3-STATE
可输出:NO封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP18,.3
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL电源:5 V
认证状态:Not Qualified座面最大高度:4.826 mm
最大待机电流:0.01 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.08 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

CY7C148-35PC 数据手册

 浏览型号CY7C148-35PC的Datasheet PDF文件第2页浏览型号CY7C148-35PC的Datasheet PDF文件第3页浏览型号CY7C148-35PC的Datasheet PDF文件第4页浏览型号CY7C148-35PC的Datasheet PDF文件第5页浏览型号CY7C148-35PC的Datasheet PDF文件第6页浏览型号CY7C148-35PC的Datasheet PDF文件第7页 
49  
CY7C148  
CY7C149  
1Kx4 Static RAM  
sion is provided by an active LOW chip select (CS) input and  
three-state outputs. The CY7C148 remains in a low-power  
mode as long as the device remains unselected; i.e., (CS) is  
HIGH, thus reducing the average power requirements of the  
device. The chip select (CS) of the CY7C149 does not affect  
the power dissipation of the device.  
Features  
• Automatic power-down when deselected (7C148)  
• CMOS for optimum speed/power  
• 25-ns access time  
• Low active power  
Writing to the device is accomplished when the chip select  
(CS) and write enable (WE) inputs are both LOW. Data on the  
I/O pins (I/O0 through I/O3) is written into the memory loca-  
tions specified on the address pins (A0 through A9).  
— 440 mW (commercial)  
— 605 mW (military)  
• Low standby power (7C148)  
— 82.5 mW (25-ns version)  
— 55 mW (all others)  
Reading the device is accomplished by taking chip select (CS)  
LOW while write enable (WE) remains HIGH. Under these  
conditions, the contents of the location specified on the  
address pins will appear on the four data I/O pins.  
5-volt power supply ± 10% tolerance, both commercial  
and military  
TTL-compatible inputs and outputs  
The I/O pins remain in a high-impedance state when chip se-  
lect (CS) is HIGH or write enable (WE) is LOW.  
Functional Description  
The CY7C148 and CY7C149 are high-performance CMOS  
static RAMs organized as 1024 by 4 bits. Easy memory expan-  
Logic Block Diagram  
PinConfigurations  
DIP  
Top View  
A
V
6
1
2
3
4
5
6
7
8
9
CC  
18  
17  
16  
15  
A
5
A
4
A
3
A
A
A
7
A
8
A
9
I/O  
I/O  
I/O  
I/O  
INPUTBUFFER  
0
1
14  
13  
12  
11  
10  
0
1
2
3
A
2
A
A
8
9
I/O  
0
CS  
WE  
GND  
A
I/O  
1
64x 64  
ARRAY  
7
A
C1482  
6
I/O  
2
LCC  
A
5
Top View  
A
4
I/O  
3
CS  
2 1 1817  
POWER  
DOWN  
(7C148)  
A
A
3
4
5
6
7
16  
4
8
COLUMN  
A
A
15  
13  
9
DECODER  
A
14 I/O  
10  
WE  
0
1
2
A
13  
12  
I/O  
I/O  
11  
A
12  
A
3
8 91011  
A A  
A
0
2
1
C1481  
C1483  
Selection Guide  
7C14825  
7C14835  
7C14845  
7C14925  
7C14935  
7C14945  
Maximum Access Time (ns)  
25  
90  
35  
80  
45  
80  
25  
90  
35  
80  
45  
80  
Maximum Operating  
Current (mA)  
Commercial  
Military  
110  
10  
110  
10  
110  
110  
Maximum Standby  
Current (mA)  
Commercial  
Military  
15  
10  
10  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05059 Rev. **  
Revised September 18, 2001  
[+] Feedback  

CY7C148-35PC 替代型号

型号 品牌 替代类型 描述 数据表
CY2147-35PC CYPRESS

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Standard SRAM, 4KX1, 35ns, CMOS, PDIP18, 0.300 INCH, PLASTIC, DIP-18
CY2148-45DC CYPRESS

功能相似

Standard SRAM, 1KX4, 45ns, CMOS, PDIP18, DIP-18
CY2148-55PC CYPRESS

功能相似

Standard SRAM, 1KX4, 55ns, CMOS, PDIP18, PLASTIC, DIP-18

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