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CY7C1482V33-200AXI PDF预览

CY7C1482V33-200AXI

更新时间： 2024-09-18 05:19:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
32页 1290K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

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中文翻译

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CY7C1482V33-200AXI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP, QFP100,.63X.87
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.71最长访问时间：3 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：200 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
内存密度：75497472 bit内存集成电路类型：CACHE SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：100
字数：4194304 words字数代码：4000000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：4MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最小待机电流：3.14 V
子类别：SRAMs最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：14 mmBase Number Matches：1

CY7C1482V33-200AXI 数据手册

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CY7C1480V33  
CY7C1482V33  
CY7C1486V33  
72-Mbit (2M x 36/4M x 18/1M x 72)  
Pipelined Sync SRAM  
Features  
Functional Description[1]  
• Supports bus operation up to 250 MHz  
• Available speed grades are 250, 200, and 167 MHz  
• Registered inputs and outputs for pipelined operation  
• 3.3V core power supply  
The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM  
integrates 2M x 36/4M x 18/1M × 72 SRAM cells with  
advanced synchronous peripheral circuitry and a two-bit  
counter for internal burst operation. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst  
Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX,  
and BWE), and Global Write (GW). Asynchronous inputs  
include the Output Enable (OE) and the ZZ pin.  
• 2.5V/3.3V I/O operation  
• Fast clock-to-output times  
— 3.0 ns (for 250 MHz device)  
• Provide high performance 3-1-1-1 access rate  
• User selectable burst counter supporting Intel®  
Pentium® interleaved or linear burst sequences  
Addresses and chip enables are registered at the rising edge  
of the clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
• Separate processor and controller address strobes  
• Synchronous self timed writes  
• Asynchronous output enable  
• Single cycle chip deselect  
Address, data inputs, and write controls are registered on-chip  
to initiate a self timed write cycle.This part supports byte write  
operations (see “Pin Definitions” on page 7 and “Truth Table”  
on page 10 for further details). Write cycles can be one to two  
or four bytes wide as controlled by the byte write control inputs.  
GW when active LOW causes all bytes to be written.  
• CY7C1480V33, CY7C1482V33 available in  
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and  
non-Pb-free 165-ball FBGA package. CY7C1486V33  
available in Pb-free and non-Pb-free 209-ball FBGA  
package  
The CY7C1480V33/CY7C1482V33/CY7C1486V33 operates  
from a +3.3V core power supply while all outputs may operate  
with either a +2.5 or +3.3V supply. All inputs and outputs are  
JEDEC standard JESD8-5 compatible.  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• “ZZ” Sleep Mode option  
Selection Guide  
250 MHz  
3.0  
200 MHz  
3.0  
167 MHz  
3.4  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
500  
500  
450  
mA  
mA  
120  
120  
120  
Note  
1. For best practices recommendations, please refer to the Cypress application note AN1064, SRAM System Guidelines.  
Cypress Semiconductor Corporation  
Document #: 38-05283 Rev. *H  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised April 23, 2007  
[+] Feedback  
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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482V33-250AXI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482V33-250BZC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482V33-250BZI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482V33-250BZXC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482V33-250BZXI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

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