Datasheet > 存储 > SRAM> CY7C1480BV25-250BZXC

CY7C1480BV25-250BZXC

更新时间： 2024-09-18 05:09:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	933K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

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CY7C1480BV25

CY7C1482BV25, CY7C1486BV25

72-Mbit (2M x 36/4M x 18/1M x 72)

Pipelined Sync SRAM

Features

Functional Description

■ Supports bus operation up to 250 MHz

■ Available speed grades are 250, 200, and 167 MHz

■ Registered inputs and outputs for pipelined operation

■ 2.5V core power supply

The

CY7C1480BV25/CY7C1482BV25/CY7C1486BV25^[1]

SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit counter

for internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE₁), depth-expansion

Chip Enables (CE₂and CE₃), Burst Control inputs (ADSC,

ADSP, and ADV), Write Enables (BW_X, and BWE), and Global

Write (GW). Asynchronous inputs include the Output Enable

(OE) and the ZZ pin.

■ 2.5V IO operation

■ Fast clock-to-output time

❐ 3.0 ns (for 250 MHz device)

■ Provide high performance 3-1-1-1 access rate

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or Address

Strobe Controller (ADSC) is active. Subsequent burst addresses

can be internally generated as controlled by the Advance pin

(ADV).

■ User selectable burst counter supporting Intel^®Pentium^®

interleaved or linear burst sequences

■ Separate processor and controller address strobes

■ Synchronous self timed writes

Address, data inputs, and write controls are registered on-chip

to initiate a self timed Write cycle. This part supports Byte Write

operations (see “Pin Definitions” on page 7 and “Truth Table” on

page 10 for further details). Write cycles can be one to two or four

bytes wide, as controlled by the byte write control inputs. When

it is active LOW, GW writes all bytes.

■ Asynchronous output enable

■ Single cycle chip deselect

■ CY7C1480BV25, CY7C1482BV25 available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and

non-Pb-free 165-ball FBGA package. CY7C1486BV25

available in Pb-free and non-Pb-free 209-ball FBGA package

■ IEEE 1149.1 JTAG-Compatible Boundary Scan

■ “ZZ” Sleep Mode option

Selection Guide

Description

Maximum Access Time

250 MHz

3.0

200 MHz

3.0

167 MHz

3.4

Unit

Maximum Operating Current

Maximum CMOS Standby Current

450

400

120

Note

1. For best practices recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

Cypress Semiconductor Corporation

Document #: 001-15143 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 29, 2008

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与CY7C1480BV25-250BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1480BV25-250BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480BV33	CYPRESS	获取价格	72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
CY7C1480BV33_11	CYPRESS	获取价格	72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
CY7C1480BV33_12	CYPRESS	获取价格	72-Mbit (2 M Ã 36/4 M Ã 18) Pipelined Sync
CY7C1480BV33-167AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480BV33-167AXI	CYPRESS	获取价格	72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
CY7C1480BV33-167AXI	INFINEON	获取价格	Synchronous SRAM
CY7C1480BV33-167BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480BV33-167BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480BV33-167BZXC	CYPRESS	获取价格	72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM

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