Datasheet > CY7C1480V25_06

CY7C1480V25_06

更新时间： 2024-09-18 05:19:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	573K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

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CY7C1480V25_06 数据手册

CY7C1480V25

CY7C1482V25

CY7C1486V25

72-Mbit (2M x 36/4M x 18/1M x 72)

Pipelined Sync SRAM

Features

Functional Description^[1]

• Supports bus operation up to 250 MHz

The CY7C1480V25/CY7C1482V25/CY7C1486V25 SRAM

integrates 2M x 36/4M x 18/1M × 72 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

• Available speed grades are 250, 200 and 167 MHz

• Registered inputs and outputs for pipelined operation

• 2.5V core power supply

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE₁), depth-expansion Chip Enables (CE₂and CE₃), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables (BW_X,

and BWE), and Global Write (GW). Asynchronous inputs

include the Output Enable (OE) and the ZZ pin.

• 2.5V/1.8V I/O operation

• Fast clock-to-output time

— 3.0 ns (for 250-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the byte write control inputs. GW when active

LOW causes all bytes to be written.

• Single Cycle Chip Deselect

• CY7C1480V25, CY7C1482V25 available in

JEDEC-standard lead-free 100-pin TQFP, lead-free and

non-lead-free 165-ball FBGA package. CY7C1486V25

available in lead-free and non-lead-free 209 ball FBGA

package.

The CY7C1480V25/CY7C1482V25/CY7C1486V25 operates

from a +2.5V core power supply while all outputs may operate

with either a +2.5 or +1.8V supply. All inputs and outputs are

JEDEC-standard JESD8-5-compatible.

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

Selection Guide

250 MHz

3.0

200 MHz

3.0

167 MHz

3.4

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

450

400

120

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com

Cypress Semiconductor Corporation

Document #: 38-05282 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 24, 2006

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与CY7C1480V25_06相关器件

型号	品牌	获取价格	描述	数据表
CY7C1480V25-167AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-167AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-167BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-167BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-167BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-167BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-200AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-200AXCT	CYPRESS	获取价格	Cache SRAM, 2MX36, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP
CY7C1480V25-200AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-200BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

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