CY7C1480BV33
CY7C1482BV33
72-Mbit (2M × 36/4M × 18)
Pipelined Sync SRAM
72-Mbit (2M
× 36/4M × 18) Pipelined Sync SRAM
Features
Functional Description
■ Supports bus operation up to 250 MHz
■ Available speed grades are 250, 200, and 167 MHz
■ Registered inputs and outputs for pipelined operation
■ 3.3 V core power supply
The CY7C1480BV33 and CY7C1482BV33 SRAM integrates
2M × 36/4M × 18 SRAM cells with advanced synchronous
peripheral circuitry and a 2-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE1), depth-expansion Chip
Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and
ADV), Write Enables (BWX, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the ZZ
pin.
■ 2.5 V/3.3 V I/O operation
■ Fast clock-to-output times
❐ 3.0 ns (for 250 MHz device)
■ Provide high performance 3-1-1-1 access rate
Addresses and chip enables are registered at the rising edge of
the clock when either address strobe processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent burst
addresses may be internally generated as controlled by the
advance pin (ADV).
■ User selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self timed writes
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see sections Pin Definitions on page 6 and Truth
Table on page 9 for further details). Write cycles can be one to
two or four bytes wide as controlled by the byte write control
inputs. GW when active LOW causes all bytes to be written.
■ Asynchronous output enable
■ Single cycle chip deselect
■ CY7C1480BV33 available in JEDEC-standard Pb-free 100-pin
thin quad flat pack (TQFP), Pb-free and non Pb-free 165-ball
fine-pitch ball grid array (FBGA) package. CY7C1482BV33
available in non Pb-free 165-ball fine-pitch ball grid array
(FBGA) package
The CY7C1480BV33 and CY7C1482BV33 operates from a
+3.3 V core power supply while all outputs may operate with
either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC
standard
JESD8-5
compatible.
For
best
practices
■ IEEE 1149.1 JTAG-compatible boundary scan
■ “ZZ” sleep mode option
recommendations, refer to the Cypress application note AN1064
“SRAM System Guidelines”.
For a complete list of related documentation, click here.
Selection Guide
Description
Maximum access time
250 MHz
3.0
200 MHz
3.0
167 MHz Unit
3.4
450
120
ns
Maximum operating current
500
500
mA
mA
Maximum CMOS standby current
120
120
Cypress Semiconductor Corporation
Document Number: 001-15145 Rev. *L
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 15, 2018