Datasheet > 存储 > SRAM> CY7C1480BV33-250BZI

CY7C1480BV33-250BZI

更新时间： 2024-11-07 09:44:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
36页	991K
描述
72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM

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技术参数
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CY7C1480BV33-250BZI 技术参数

是否Rohs认证：	不符合	生命周期：	Active
零件包装代码：	BGA	包装说明：	LBGA, BGA165,11X15,40
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
Factory Lead Time：	1 week	风险等级：	2.08
Is Samacsys：	N	最长访问时间：	3 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	250 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	17 mm
内存密度：	75497472 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	36	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	2097152 words	字数代码：	2000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	2MX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	220
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.5 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD SILVER	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	15 mm
Base Number Matches：	1

CY7C1480BV33-250BZI 数据手册

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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33

72-Mbit (2 M × 36/4 M × 18/1 M × 72)

Pipelined Sync SRAM

72-Mbit (2

M × 36/4 M × 18/1 M × 72) Pipelined Sync SRAM

Features

Functional Description

■ Supports bus operation up to 250 MHz

The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33

SRAM integrates 2 M × 36/4 M × 18/1 M × 72 SRAM cells with

■ Available speed grades are 250, 200, and 167 MHz

■ Registered inputs and outputs for pipelined operation

■ 3.3 V core power supply

advanced synchronous peripheral circuitry and a 2-bit counter

for internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE₁), depth-expansion

Chip Enables (CE₂and CE₃), Burst Control inputs (ADSC,

ADSP, and ADV), Write Enables (BW_X, and BWE), and Global

Write (GW). Asynchronous inputs include the Output Enable

(OE) and the ZZ pin.

■ 2.5 V/3.3 V I/O operation

■ Fast clock-to-output times

❐ 3.0 ns (for 250 MHz device)

■ Provide high performance 3-1-1-1 access rate

Addresses and chip enables are registered at the rising edge of

the clock when either address strobe processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent burst

addresses may be internally generated as controlled by the

advance pin (ADV).

■ User selectable burst counter supporting Intel^®Pentium^®

interleaved or linear burst sequences

■ Separate processor and controller address strobes

■ Synchronous self timed writes

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle.This part supports byte write

operations (see sections Pin Definitions on page 8 and Truth

Table on page 11 for further details). Write cycles can be one to

two or four bytes wide as controlled by the byte write control

inputs. GW when active LOW causes all bytes to be written.

■ Asynchronous output enable

■ Single cycle chip deselect

■ CY7C1480BV33, CY7C1482BV33 available in JEDEC-

standard Pb-free 100-pin thin quad flat pack (TQFP), Pb-free

and non Pb-free 165-ball fine-pitch ball grid array (FBGA)

package. CY7C1486BV33 available in Pb-free and

non-Pb-free 209-ball FBGA package

The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33

operates from a +3.3 V core power supply while all outputs may

operate with either a +2.5 or +3.3 V supply. All inputs and outputs

are JEDEC standard JESD8-5 compatible. For best practices

recommendations, refer to the Cypress application note AN1064

“SRAM System Guidelines”.

■ IEEE 1149.1 JTAG-compatible boundary scan

■ “ZZ” sleep mode option

Selection Guide

Description

Maximum access time

250 MHz

3.0

200 MHz

3.0

167 MHz

3.4

Unit

Maximum operating current

500

450

Maximum CMOS standby current

120

Cypress Semiconductor Corporation

Document Number: 001-15145 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 30, 2011

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CY7C1480BV33-250BZI 替代型号

型号	品牌	替代类型	描述	数据表
CY7C1480BV33-200BZXI	CYPRESS	完全替代	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480BV33-167BZI	CYPRESS	类似代替	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

与CY7C1480BV33-250BZI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1480BV33-250BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480BV33-250BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25_06	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-167AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-167AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-167BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-167BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-167BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-167BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

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