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CY7C1480BV25-250BZXI PDF预览

CY7C1480BV25-250BZXI

更新时间： 2024-09-18 05:09:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
31页 933K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

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中文翻译

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CY7C1480BV25-250BZXI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：LBGA, BGA165,11X15,40针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.48
Is Samacsys：N最长访问时间：3 ns
最大时钟频率 (fCLK)：250 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：17 mm内存密度：75497472 bit
内存集成电路类型：CACHE SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：165字数：2097152 words
字数代码：2000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：2MX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5 V
认证状态：Not Qualified座面最大高度：1.4 mm
最小待机电流：2.38 V子类别：SRAMs
最大压摆率：0.45 mA最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：40
宽度：15 mmBase Number Matches：1

CY7C1480BV25-250BZXI 数据手册

 浏览型号CY7C1480BV25-250BZXI的Datasheet PDF文件第2页浏览型号CY7C1480BV25-250BZXI的Datasheet PDF文件第3页浏览型号CY7C1480BV25-250BZXI的Datasheet PDF文件第4页浏览型号CY7C1480BV25-250BZXI的Datasheet PDF文件第5页浏览型号CY7C1480BV25-250BZXI的Datasheet PDF文件第6页浏览型号CY7C1480BV25-250BZXI的Datasheet PDF文件第7页 
CY7C1480BV25  
CY7C1482BV25, CY7C1486BV25  
72-Mbit (2M x 36/4M x 18/1M x 72)  
Pipelined Sync SRAM  
Features  
Functional Description  
■ Supports bus operation up to 250 MHz  
■ Available speed grades are 250, 200, and 167 MHz  
■ Registered inputs and outputs for pipelined operation  
■ 2.5V core power supply  
The  
CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1]  
SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with  
advanced synchronous peripheral circuitry and a two-bit counter  
for internal burst operation. All synchronous inputs are gated by  
registers controlled by a positive-edge-triggered Clock Input  
(CLK). The synchronous inputs include all addresses, all data  
inputs, address-pipelining Chip Enable (CE1), depth-expansion  
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,  
ADSP, and ADV), Write Enables (BWX, and BWE), and Global  
Write (GW). Asynchronous inputs include the Output Enable  
(OE) and the ZZ pin.  
■ 2.5V IO operation  
■ Fast clock-to-output time  
❐ 3.0 ns (for 250 MHz device)  
■ Provide high performance 3-1-1-1 access rate  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or Address  
Strobe Controller (ADSC) is active. Subsequent burst addresses  
can be internally generated as controlled by the Advance pin  
(ADV).  
■ User selectable burst counter supporting Intel® Pentium®  
interleaved or linear burst sequences  
■ Separate processor and controller address strobes  
■ Synchronous self timed writes  
Address, data inputs, and write controls are registered on-chip  
to initiate a self timed Write cycle. This part supports Byte Write  
operations (see “Pin Definitions” on page 7 and “Truth Table” on  
page 10 for further details). Write cycles can be one to two or four  
bytes wide, as controlled by the byte write control inputs. When  
it is active LOW, GW writes all bytes.  
■ Asynchronous output enable  
■ Single cycle chip deselect  
■ CY7C1480BV25, CY7C1482BV25 available in  
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and  
non-Pb-free 165-ball FBGA package. CY7C1486BV25  
available in Pb-free and non-Pb-free 209-ball FBGA package  
■ IEEE 1149.1 JTAG-Compatible Boundary Scan  
■ “ZZ” Sleep Mode option  
Selection Guide  
Description  
Maximum Access Time  
250 MHz  
3.0  
200 MHz  
3.0  
167 MHz  
3.4  
Unit  
ns  
Maximum Operating Current  
Maximum CMOS Standby Current  
450  
450  
400  
mA  
mA  
120  
120  
120  
Note  
1. For best practices recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.  
Cypress Semiconductor Corporation  
Document #: 001-15143 Rev. *D  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised February 29, 2008  
[+] Feedback  
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