Datasheet > 存储 > SRAM> CY7C1471V25-100BZC

CY7C1471V25-100BZC

更新时间： 2024-11-15 22:37:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
30页	373K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture

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CY7C1471V25-100BZC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.91	Is Samacsys：	N
最长访问时间：	8.5 ns	其他特性：	FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：	100 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	17 mm	内存密度：	75497472 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	2097152 words
字数代码：	2000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	2MX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	220	电源：	1.8/2.5,2.5 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最小待机电流：	2.38 V	子类别：	SRAMs
最大供电电压 (Vsup)：	2.625 V	最小供电电压 (Vsup)：	2.375 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	15 mm
Base Number Matches：	1

CY7C1471V25-100BZC 数据手册

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CY7C1471V25

CY7C1473V25

CY7C1475V25

PRELIMINARY

72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM

with NoBL™ Architecture

Features

Functional Description^[1]

• No Bus Latency™ (NoBL™) architecture eliminates

dead cycles between write and read cycles.

The CY7C1471V25, CY7C1473V25 and CY7C1475V25 are

2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through

Burst SRAMs designed specifically to support unlimited true

back-to-back Read/Write operations without the insertion of

wait states. The CY7C1471V25, CY7C1473V25 and

CY7C1475V25 are equipped with the advanced No Bus

Latency (NoBL) logic required to enable consecutive

Read/Write operations with data being transferred on every

clock cycle. This feature dramatically improves the throughput

of data through the SRAM, especially in systems that require

frequent Write-Read transitions.

• Can support up to 133-MHz bus operations with zero

wait states

• Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).

• 2.5V/1.8V I/O power supply

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

— 8.5 ns (for 100-MHz device)

Write operations are controlled by the two or four Byte Write

Select (BW_X) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

• Clock Enable (CEN) pin to enable clock and suspend

operation

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

• Synchronous self-timed writes

• Asynchronous Output Enable

• Offered in JEDEC-standard lead-free 100 TQFP, and

165-ball fBGA packages for CY7C1471V25 and

CY7C1473V25. 209-ball fBGA package for

CY7C1475V25.

• Three chip enables for simple depth expansion.

• Automatic Power-down feature available using ZZ

mode or CE deselect.

• JTAG boundary scan for BGA and fBGA packages

• Burst Capability—linear or interleaved burst order

• Low standby power

Selection Guide

133 MHz

6.5

100 MHz

8.5

Unit

Maximum Access Time

Maximum Operating Current

305

275

Maximum CMOS Standby Current

120

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05287 Rev. *E

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised December 5, 2004

12 3 4 5 6 7...30

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与CY7C1471V25-100BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1471V25-100BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471V25-100BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V25-100BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471V25-117BGC	CYPRESS	获取价格	ZBT SRAM, 2MX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1471V25-133AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V25-133AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471V25-133BGC	CYPRESS	获取价格	ZBT SRAM, 2MX36, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1471V25-133BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V25-133BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471V25-133BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture

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