CY7C1471V33-133AXC

更新时间： 2024-11-06 21:58:03

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
29页	376K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1471V33-133AXC 数据手册

浏览型号CY7C1471V33-133AXC的Datasheet PDF文件第2页

浏览型号CY7C1471V33-133AXC的Datasheet PDF文件第3页

浏览型号CY7C1471V33-133AXC的Datasheet PDF文件第4页

浏览型号CY7C1471V33-133AXC的Datasheet PDF文件第5页

浏览型号CY7C1471V33-133AXC的Datasheet PDF文件第6页

CY7C1471V33

CY7C1473V33

CY7C1475V33

PRELIMINARY

72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through

SRAM with NoBL™ Architecture

• JTAG boundary scan for BGA and fBGA packages

• Burst Capability—linear or interleaved burst order

Features

• No Bus Latency™ (NoBL™) architecture eliminates

dead cycles between write and read cycles.

• Low standby power

Functional Description^[1]

• Can support up to 133-MHz bus operations with zero

wait states

The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are

3.3V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through

Burst SRAMs designed specifically to support unlimited true

back-to-back Read/Write operations without the insertion of

wait states. The CY7C1471V33, CY7C1473V33 and

CY7C1475V33 are equipped with the advanced No Bus

Latency (NoBL) logic required to enable consecutive

Read/Write operations with data being transferred on every

clock cycle. This feature dramatically improves the throughput

of data through the SRAM, especially in systems that require

frequent Write-Read transitions.

• Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

• 3.3V/2.5V I/O power supply

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

— 8.5 ns (for 100-MHz device)

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).

• Clock Enable (CEN) pin to enable clock and suspend

operation

• Synchronous self-timed writes

• Asynchronous Output Enable

Write operations are controlled by the two or four Byte Write

Select (BW_X) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

• Offered in JEDEC-standard lead-free 100 TQFP, and

165-ball fBGA packages for CY7C1471V33 and

CY7C1473V33. 209-ball fBGA package for

CY7C1475V33.

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

• Three chip enables for simple depth expansion.

• Automatic Power-down feature available using ZZ

mode or CE deselect.

Selection Guide

133 MHz

6.5

100 MHz

8.5

Unit

Maximum Access Time

Maximum Operating Current

335

305

Maximum CMOS Standby Current

150

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05288 Rev. *E

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised December 5, 2004

12 3 4 5 6 7...29

中文翻译

下载PDF

与CY7C1471V33-133AXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1471V33-133AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471V33-133BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V33-133BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471V33-133BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V33-133BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C147-25LC	ETC	获取价格	x1 SRAM
CY7C147-25PC	CYPRESS	获取价格	4K x 1 STATIC RAM
CY7C1472BV25	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1472BV25-167AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1472BV25-167AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S

与CY7C1471V33-133AXC相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

16
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

13
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

37
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

34

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1471V33-133AXC

CY7C1471V33-133AXC 数据手册

与CY7C1471V33-133AXC相关器件

与CY7C1471V33-133AXC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1471V33-133AXC

CY7C1471V33-133AXC 数据手册

与CY7C1471V33-133AXC相关器件

与CY7C1471V33-133AXC相关文章

您还可以找

您在本页遇到什么问题？