CY7C1471V33
CY7C1473V33
CY7C1475V33
72-Mbit (2M x 36/4M x 18/1M x 72)
Flow-ThroughSRAMwithNoBL™Architecture
Functional Description [1]
Features
• No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are
3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst
SRAMs designed specifically to support unlimited true
back-to-back read or write operations without the insertion of
wait states. The CY7C1471V33, CY7C1473V33 and
CY7C1475V33 are equipped with the advanced No Bus
Latency (NoBL) logic required to enable consecutive read or
write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of
data through the SRAM, especially in systems that require
frequent write-read transitions.
• Supportsupto133MHzbusoperationswithzerowaitstates
• Data is transferred on every clock
• PincompatibleandfunctionallyequivalenttoZBT™devices
• Internally self timed output buffer control to eliminate the
need to use OE
• Registered inputs for flow through operation
• Byte Write capability
• 3.3V/2.5V IO supply (VDDQ
)
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock
cycle.Maximum access delay from the clock rise is 6.5 ns
(133-MHz device).
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend
operation
• Synchronous self timed writes
Write operations are controlled by two or four Byte Write Select
(BWX) and a Write Enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
• Asynchronous Output Enable (OE)
• CY7C1471V33, CY7C1473V33 available in
JEDEC-standard Pb-free 100-Pin TQFP, Pb-free and
non-Pb-free 165-Ball FBGA package. CY7C1475V33
available in Pb-free and non-Pb-free 209-Ball FBGA
package
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
• Three Chip Enables (CE1, CE2, CE3) for simple depth
expansion
• Automatic power down feature available using ZZ mode or
CE deselect
• IEEE 1149.1 JTAG Boundary Scan compatible
• Burst Capability — linear or interleaved burst order
• Low standby power
Selection Guide
133 MHz
6.5
117 MHz
8.5
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
305
275
mA
mA
120
120
Note
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 38-05288 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 04, 2007
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