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CY7C1472BV25-250BZC PDF预览

CY7C1472BV25-250BZC

更新时间： 2024-01-11 15:24:50
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
29页 868K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture

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CY7C1472BV25-250BZC 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：BGA包装说明：LBGA, BGA165,11X15,40
针数：165Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.51Is Samacsys：N
最长访问时间：3 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：250 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：17 mm内存密度：75497472 bit
内存集成电路类型：ZBT SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：165字数：4194304 words
字数代码：4000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：4MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5 V
认证状态：Not Qualified座面最大高度：1.4 mm
最小待机电流：2.38 V子类别：SRAMs
最大压摆率：0.45 mA最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：40
宽度：15 mmBase Number Matches：1

CY7C1472BV25-250BZC 数据手册

 浏览型号CY7C1472BV25-250BZC的Datasheet PDF文件第2页浏览型号CY7C1472BV25-250BZC的Datasheet PDF文件第3页浏览型号CY7C1472BV25-250BZC的Datasheet PDF文件第4页浏览型号CY7C1472BV25-250BZC的Datasheet PDF文件第5页浏览型号CY7C1472BV25-250BZC的Datasheet PDF文件第6页浏览型号CY7C1472BV25-250BZC的Datasheet PDF文件第7页 
CY7C1470BV25  
CY7C1472BV25, CY7C1474BV25  
72-Mbit (2M x 36/4M x 18/1M x 72)  
Pipelined SRAM with NoBL™ Architecture  
Features  
Functional Description  
■ Pin-compatible and functionally equivalent to ZBT™  
The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25  
are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous pipelined burst  
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.  
They are designed to support unlimited true back-to-back read  
or write operations with no wait states. The CY7C1470BV25,  
■ Supports 250 MHz bus operations with zero wait states  
❐ Available speed grades are 250, 200, and 167 MHz  
■ Internally self-timed output buffer control to eliminate the need  
CY7C1472BV25, and CY7C1474BV25 are equipped with the  
advanced (NoBL) logic required to enable consecutive read or  
write operations with data being transferred on every clock cycle.  
This feature dramatically improves the throughput of data in  
systems that require frequent read or write transitions. The  
CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are  
pin-compatible and functionally equivalent to ZBT devices.  
to use asynchronous OE  
■ Fully registered (inputs and outputs) for pipelined operation  
■ Byte Write capability  
■ Single 2.5V power supply  
■ 2.5V IO supply (VDDQ  
)
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. All data outputs pass through output  
registers controlled by the rising edge of the clock. The clock  
input is qualified by the Clock Enable (CEN) signal, which when  
deasserted suspends operation and extends the previous clock  
cycle. Write operations are controlled by the Byte Write Selects  
■ Fast clock-to-output times  
❐ 3.0 ns (for 250-MHz device)  
■ Clock Enable (CEN) pin to suspend operation  
■ Synchronous self-timed writes  
(BWa–BWd  
for  
CY7C1470BV25,  
BWa–BWb  
for  
■ CY7C1470BV25, CY7C1472BV25 available in  
CY7C1472BV25, and BWa–BWh for CY7C1474BV25) and a  
Write Enable (WE) input. All writes are conducted with on-chip  
synchronous self-timed write circuitry.  
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and  
non-Pb-free 165-ball FBGA package. CY7C1474BV25  
available in Pb-free and non-Pb-free 209-ball FBGA package  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. To avoid bus contention,  
the output drivers are synchronously tri-stated during the data  
portion of a write sequence.  
■ IEEE 1149.1 JTAG Boundary Scan compatible  
■ Burst capability—linear or interleaved burst order  
■ “ZZ” Sleep Mode option and Stop Clock option  
Selection Guide  
Description  
Maximum Access Time  
250 MHz  
200 MHz  
3.0  
167 MHz  
3.4  
Unit  
ns  
3.0  
450  
120  
Maximum Operating Current  
450  
400  
mA  
mA  
Maximum CMOS Standby Current  
120  
120  
Cypress Semiconductor Corporation  
Document #: 001-15032 Rev. *D  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised February 29, 2008  
[+] Feedback  
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