Datasheet > CY7C1471V33_12

CY7C1471V33_12

更新时间： 2024-11-16 12:21:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
22页	680K
描述
72-Mbit (2 M Ã 36) Flow-Through SRAM with NoBLâ¢ Architecture

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CY7C1471V33_12 数据手册

CY7C1471V33

72-Mbit (2 M × 36) Flow-Through SRAM with

NoBL™ Architecture

72-Mbit (2

M × 36) Flow-Through SRAM with NoBL™ Architecture

Features

Functional Description

■ No Bus Latency™ (NoBL™) architecture eliminates dead

cycles between write and read cycles

The CY7C1471V33 is 3.3 V, 2 M × 36 synchronous flow through

burst SRAMs designed specifically to support unlimited true

back-to-back read or write operations without the insertion of

wait states. The CY7C1471V33 is equipped with the advanced

No Bus Latency (NoBL) logic required to enable consecutive

read or write operations with data being transferred on every

clock cycle. This feature dramatically improves the throughput of

data through the SRAM, especially in systems that require

frequent write-read transitions.

■ Supports up to 133 MHz bus operations with zero wait states

■ Data is transferred on every clock

■ Pin compatible and functionally equivalent to ZBT™ devices

■ Internally self timed output buffer control to eliminate the need

to use OE

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock input is qualified by the

clock enable (CEN) signal, which when deasserted suspends

operation and extends the previous clock cycle.Maximum

access delay from the clock rise is 6.5 ns (133-MHz device).

■ Registered inputs for flow through operation

■ Byte Write capability

■ 3.3 V/2.5 V I/O supply (V_DDQ

)

■ Fast clock-to-output times

❐ 6.5 ns (for 133-MHz device)

Write operations are controlled by two or four byte write select

(BW_X) and a write enable (WE) input. All writes are conducted

with on-chip synchronous self timed write circuitry.

■ Clock enable (CEN) pin to enable clock and suspend operation

■ Synchronous self timed writes

Three synchronous chip enables (CE₁, CE₂, CE₃) and an

asynchronous output enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

■ Asynchronous output enable (OE)

■ CY7C1471V33 available in JEDEC-standard Pb-free 100-pin

TQFP

■ Three chip enables (CE₁, CE₂, CE₃) for simple depth

expansion

■ Automatic power down feature available using ZZ mode or CE

deselect

■ Burst capability – linear or interleaved burst order

■ Low standby power

Selection Guide

Description

Maximum access time

133 MHz Unit

6.5

305

120

Maximum operating current

Maximum CMOS standby current

Cypress Semiconductor Corporation

Document Number: 38-05288 Rev. *N

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 1, 2012

12 3 4 5 6 7...22

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与CY7C1471V33_12相关器件

型号	品牌	获取价格	描述	数据表
CY7C1471V33_13	CYPRESS	获取价格	72-Mbit (2 M x 36) Flow-Through SRAM with NoB
CY7C1471V33-100AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V33-100AXI	CYPRESS	获取价格	ZBT SRAM, 2MX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, TQF
CY7C1471V33-100BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V33-100BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V33-100BZXI	CYPRESS	获取价格	ZBT SRAM, 2MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
CY7C1471V33-117AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471V33-117AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471V33-117BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471V33-117BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug

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