CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through
SRAM with NoBL™ Architecture
• JTAG boundary scan for BGA and fBGA packages
• Burst Capability—linear or interleaved burst order
Features
• No Bus Latency™ (NoBL™) architecture eliminates
dead cycles between write and read cycles.
• Low standby power
Functional Description[1]
• Can support up to 133-MHz bus operations with zero
wait states
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are
3.3V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through
Burst SRAMs designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1471V33, CY7C1473V33 and
CY7C1475V33 are equipped with the advanced No Bus
Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write-Read transitions.
• Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 3.3V/2.5V I/O power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 8.5 ns (for 100-MHz device)
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
• Clock Enable (CEN) pin to enable clock and suspend
operation
• Synchronous self-timed writes
• Asynchronous Output Enable
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
• Offered in JEDEC-standard lead-free 100 TQFP, and
165-ball fBGA packages for CY7C1471V33 and
CY7C1473V33. Lead-free 209-ball fBGA package for
CY7C1475V33.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
• Three chip enables for simple depth expansion.
• Automatic Power-down feature available using ZZ
mode or CE deselect.
Selection Guide
133 MHz
6.5
100 MHz
8.5
Unit
ns
Maximum Access Time
Maximum Operating Current
335
305
mA
mA
Maximum CMOS Standby Current
150
150
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05288 Rev. *G
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised March 10, 2005
5秒后页面跳转
AO3401场效应管参数、引脚图、应用原理图
BT131可控硅参数及引脚图、工作原理详解
74LS32芯片参数、引脚图及功能真值表
全球首块英伟达H200交付 黄仁勋“送货上门”
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
