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CY7C1471V33-117BZXC PDF预览

CY7C1471V33-117BZXC

更新时间： 2024-02-06 11:17:50
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
32页 1141K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL⑩ Architecture

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CY7C1471V33-117BZXC 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：LBGA, BGA165,11X15,40
针数：165Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.8最长访问时间：8.5 ns
其他特性：FLOW-THROUGH ARCHITECTURE最大时钟频率 (fCLK)：117 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B165
JESD-609代码：e1长度：17 mm
内存密度：75497472 bit内存集成电路类型：ZBT SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：165
字数：2097152 words字数代码：2000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：2MX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.4 mm最小待机电流：3.14 V
子类别：SRAMs最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：15 mmBase Number Matches：1

CY7C1471V33-117BZXC 数据手册

 浏览型号CY7C1471V33-117BZXC的Datasheet PDF文件第2页浏览型号CY7C1471V33-117BZXC的Datasheet PDF文件第3页浏览型号CY7C1471V33-117BZXC的Datasheet PDF文件第4页浏览型号CY7C1471V33-117BZXC的Datasheet PDF文件第5页浏览型号CY7C1471V33-117BZXC的Datasheet PDF文件第6页浏览型号CY7C1471V33-117BZXC的Datasheet PDF文件第7页 
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
72-Mbit (2M x 36/4M x 18/1M x 72)  
Flow-ThroughSRAMwithNoBL™Architecture  
Functional Description [1]  
Features  
• No Bus Latency™ (NoBL™) architecture eliminates dead  
cycles between write and read cycles  
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are  
3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst  
SRAMs designed specifically to support unlimited true  
back-to-back read or write operations without the insertion of  
wait states. The CY7C1471V33, CY7C1473V33 and  
CY7C1475V33 are equipped with the advanced No Bus  
Latency (NoBL) logic required to enable consecutive read or  
write operations with data being transferred on every clock  
cycle. This feature dramatically improves the throughput of  
data through the SRAM, especially in systems that require  
frequent write-read transitions.  
• Supportsupto133MHzbusoperationswithzerowaitstates  
• Data is transferred on every clock  
• PincompatibleandfunctionallyequivalenttoZBT™devices  
• Internally self timed output buffer control to eliminate the  
need to use OE  
• Registered inputs for flow through operation  
• Byte Write capability  
• 3.3V/2.5V IO supply (VDDQ  
)
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. The clock input is qualified by  
the Clock Enable (CEN) signal, which when deasserted  
suspends operation and extends the previous clock  
cycle.Maximum access delay from the clock rise is 6.5 ns  
(133-MHz device).  
• Fast clock-to-output times  
— 6.5 ns (for 133-MHz device)  
• Clock Enable (CEN) pin to enable clock and suspend  
operation  
• Synchronous self timed writes  
Write operations are controlled by two or four Byte Write Select  
(BWX) and a Write Enable (WE) input. All writes are conducted  
with on-chip synchronous self timed write circuitry.  
• Asynchronous Output Enable (OE)  
• CY7C1471V33, CY7C1473V33 available in  
JEDEC-standard Pb-free 100-Pin TQFP, Pb-free and  
non-Pb-free 165-Ball FBGA package. CY7C1475V33  
available in Pb-free and non-Pb-free 209-Ball FBGA  
package  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. To avoid bus contention,  
the output drivers are synchronously tri-stated during the data  
portion of a write sequence.  
• Three Chip Enables (CE1, CE2, CE3) for simple depth  
expansion  
• Automatic power down feature available using ZZ mode or  
CE deselect  
• IEEE 1149.1 JTAG Boundary Scan compatible  
• Burst Capability — linear or interleaved burst order  
• Low standby power  
Selection Guide  
133 MHz  
6.5  
117 MHz  
8.5  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
305  
275  
mA  
mA  
120  
120  
Note  
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.  
Cypress Semiconductor Corporation  
Document #: 38-05288 Rev. *J  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 04, 2007  
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