Datasheet > CY7C143-25JC

CY7C143-25JC

更新时间： 2024-11-30 22:03:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	551K
描述
2K x 16 Dual-Port Static RAM

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中文翻译

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技术参数
数据手册

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CY7C143-25JC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	LCC	包装说明：	QCCJ, LDCC68,1.0SQ
针数：	68	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.41
风险等级：	5.41	Base Number Matches：	1

CY7C143-25JC 数据手册

CY7C133

CY7C143

2K x 16 Dual-Port Static RAM

Features

Functional Description

• True dual-ported memory cells which allow

The CY7C133 and CY7C143 are high-speed CMOS 2K by 16

dual-port static RAMs. Two ports are provided permitting

independent access to any location in memory. The CY7C133

can be utilized as either a stand-alone 16-bit dual-port static

RAM or as a master dual-port RAM in conjunction with the

CY7C143 slave dual-port device in systems requiring 32-bit or

greater word widths. It is the solution to applications requiring

shared or buffered data, such as cache memory for DSP,

bit-slice, or multiprocessor designs.

simultaneous reads of the same memory location

• 2K x 16 organization

• 0.65-micron CMOS for optimum speed/power

• High-speed access: 25/35/55 ns

• Low operating power: I_CC= 150 mA (typ.)

• Fully asynchronous operation

• Master CY7C133 expands data bus width to 32 bits or

more using slave CY7C143

• BUSY output flag on CY7C133; BUSY input flag on

CY7C143

• Available in 68-pin PLCC

Each port has independent control pins; Chip Enable (CE),

Write Enable (R/W_UB, R/W_LB), and Output Enable (OE).

BUSY signals that the port is trying to access the same

location currently being accessed by the other port. An

automatic power-down feature is controlled independently on

each port by the Chip Enable (CE) pin.

The CY7C133 and CY7C143 are available in 68-pin PLCC.

Logic Block Diagram

R/W

LUB

R/W

RUB

R/W

RLB

R/W

LLB

I/O – I/O

15L

15R

I/O

CONTROL

I/O

CONTROL

I/O – I/O

]

^[1

[1]

BUSY

10L

10R

ADDRESS

DECODER

ADDRESS

DECODER

MEMORY

ARRAY

ARBITRATION

LOGIC

(CY7C133 ONLY)

R/W

RUB

RLB

LUB

R/W

LLB

Note:

1. CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input.

Cypress Semiconductor Corporation

Document #: 38-06036 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised June 22, 2004

12 3 4 5 6 7...13

中文翻译

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与CY7C143-25JC相关器件

型号	品牌	获取价格	描述	数据表
CY7C143-25JCR	CYPRESS	获取价格	Dual-Port SRAM, 2KX16, 25ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C143-25JI	CYPRESS	获取价格	2K x 16 Dual-Port Static RAM
CY7C143-25JIR	CYPRESS	获取价格	Dual-Port SRAM, 2KX16, 25ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C143-35JC	CYPRESS	获取价格	2K x 16 Dual-Port Static RAM
CY7C143-35JCR	CYPRESS	获取价格	Dual-Port SRAM, 2KX16, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C143-35JI	CYPRESS	获取价格	2K x 16 Dual-Port Static RAM
CY7C143-35JIR	CYPRESS	获取价格	Dual-Port SRAM, 2KX16, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C143-35JIT	CYPRESS	获取价格	Dual-Port SRAM, 2KX16, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C143-55JC	CYPRESS	获取价格	2K x 16 Dual-Port Static RAM
CY7C143-55JC	ROCHESTER	获取价格	2KX16 DUAL-PORT SRAM, 55ns, PQCC68, PLASTIC, LCC-68

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