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CY7C1440AV25-200BZXC PDF预览

CY7C1440AV25-200BZXC

更新时间: 2024-12-01 05:19:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
32页 525K
描述
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

CY7C1440AV25-200BZXC 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:BGA
包装说明:15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165针数:165
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.8
Is Samacsys:N最长访问时间:3.2 ns
其他特性:PIPELINED ARCHITECTURE最大时钟频率 (fCLK):200 MHz
I/O 类型:COMMONJESD-30 代码:R-PBGA-B165
JESD-609代码:e1长度:17 mm
内存密度:37748736 bit内存集成电路类型:CACHE SRAM
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:165
字数:1048576 words字数代码:1000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1MX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装等效代码:BGA165,11X15,40
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:1.8/2.5,2.5 V认证状态:Not Qualified
座面最大高度:1.4 mm最小待机电流:2.38 V
子类别:SRAMs最大压摆率:0.385 mA
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:20宽度:15 mm
Base Number Matches:1

CY7C1440AV25-200BZXC 数据手册

 浏览型号CY7C1440AV25-200BZXC的Datasheet PDF文件第2页浏览型号CY7C1440AV25-200BZXC的Datasheet PDF文件第3页浏览型号CY7C1440AV25-200BZXC的Datasheet PDF文件第4页浏览型号CY7C1440AV25-200BZXC的Datasheet PDF文件第5页浏览型号CY7C1440AV25-200BZXC的Datasheet PDF文件第6页浏览型号CY7C1440AV25-200BZXC的Datasheet PDF文件第7页 
CY7C1440AV25  
CY7C1442AV25  
CY7C1446AV25  
36-Mbit (1M x 36/2M x 18/512K x 72)  
Pipelined Sync SRAM  
Features  
Functional Description[1]  
• Supports bus operation up to 250 MHz  
The CY7C1440AV25/CY7C1442AV25/CY7C1446AV25 SRAM  
integrates 1M x 36/2M x 18/512K x 72 SRAM cells with  
advanced synchronous peripheral circuitry and a two-bit  
• Available speed grades are 250, 200 and 167 MHz  
• Registered inputs and outputs for pipelined operation  
• 2.5V core power supply  
counter for internal burst operation. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst  
Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX,  
and BWE), and Global Write (GW). Asynchronous inputs  
include the Output Enable (OE) and the ZZ pin.  
• 2.5V/1.8V I/O powersupply  
• Fast clock-to-output times  
— 2.6 ns (for 250-MHz device)  
• Provide high-performance 3-1-1-1 access rate  
User-selectable burst counter supporting Intel®  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
Pentium® interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous output enable  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to two or four bytes wide as  
controlled by the byte write control inputs. GW when active  
• Single-cycle Chip Deselect  
• CY7C1440AV25, CY7C1442AV25 available in  
JEDEC-standard lead-free 100-pin TQFP package,  
lead-free and non-lead-free 165-ball FBGA package.  
CY7C1446AV25availableinlead-freeandnon-lead-free  
209-ball FBGA package  
causes all bytes to be written.  
LOW  
The  
CY7C1440AV25/CY7C1442AV25/CY7C1446AV25  
operates from a +2.5V core power supply while all outputs  
may operate with a +2.5V/1.8V supply. All inputs and outputs  
are JEDEC-standard JESD8-5-compatible.  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• “ZZ” Sleep Mode Option  
Selection Guide  
250 MHz  
2.6  
200 MHz  
3.2  
167 MHz  
3.4  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
435  
385  
335  
mA  
mA  
Maximum CMOS Standby Current  
120  
120  
120  
Notes:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05350 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 21, 2006  

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