5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> CY7C143-35JC
CY7C143-35JC PDF预览

CY7C143-35JC

更新时间： 2024-11-30 22:03:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
13页 551K
描述
2K x 16 Dual-Port Static RAM

阅读下载

中文翻译

获取价格

CY7C143-35JC 数据手册

 浏览型号CY7C143-35JC的Datasheet PDF文件第2页浏览型号CY7C143-35JC的Datasheet PDF文件第3页浏览型号CY7C143-35JC的Datasheet PDF文件第4页浏览型号CY7C143-35JC的Datasheet PDF文件第5页浏览型号CY7C143-35JC的Datasheet PDF文件第6页浏览型号CY7C143-35JC的Datasheet PDF文件第7页 
CY7C133  
CY7C143  
2K x 16 Dual-Port Static RAM  
Features  
Functional Description  
• True dual-ported memory cells which allow  
The CY7C133 and CY7C143 are high-speed CMOS 2K by 16  
dual-port static RAMs. Two ports are provided permitting  
independent access to any location in memory. The CY7C133  
can be utilized as either a stand-alone 16-bit dual-port static  
RAM or as a master dual-port RAM in conjunction with the  
CY7C143 slave dual-port device in systems requiring 32-bit or  
greater word widths. It is the solution to applications requiring  
shared or buffered data, such as cache memory for DSP,  
bit-slice, or multiprocessor designs.  
simultaneous reads of the same memory location  
• 2K x 16 organization  
• 0.65-micron CMOS for optimum speed/power  
• High-speed access: 25/35/55 ns  
• Low operating power: ICC = 150 mA (typ.)  
• Fully asynchronous operation  
• Master CY7C133 expands data bus width to 32 bits or  
more using slave CY7C143  
• BUSY output flag on CY7C133; BUSY input flag on  
CY7C143  
• Available in 68-pin PLCC  
Each port has independent control pins; Chip Enable (CE),  
Write Enable (R/WUB, R/WLB), and Output Enable (OE).  
BUSY signals that the port is trying to access the same  
location currently being accessed by the other port. An  
automatic power-down feature is controlled independently on  
each port by the Chip Enable (CE) pin.  
The CY7C133 and CY7C143 are available in 68-pin PLCC.  
Logic Block Diagram  
CE  
R
CE  
L
R/W  
LUB  
R/W  
RUB  
R/W  
RLB  
R/W  
LLB  
OE  
R
OE  
L
I/O – I/O  
I/O – I/O  
8R  
8L  
15L  
15R  
I/O  
CONTROL  
I/O  
CONTROL  
I/O – I/O  
0L  
I/O – I/O  
0R  
7L  
7R  
]
[1  
[1]  
BUSY  
BUSY  
L
R
A
A
10L  
10R  
0R  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
MEMORY  
ARRAY  
A
0L  
A
ARBITRATION  
LOGIC  
CE  
OE  
CE  
L
L
R
OE  
R
(CY7C133 ONLY)  
R/W  
R/W  
RUB  
RLB  
LUB  
R/W  
R/W  
LLB  
Note:  
1. CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input.  
Cypress Semiconductor Corporation  
Document #: 38-06036 Rev. *B  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised June 22, 2004  
1234567...13

中文翻译

下载PDF

与CY7C143-35JC相关器件

型号 品牌 获取价格 描述 数据表
CY7C143-35JCR CYPRESS

获取价格

 		Dual-Port SRAM, 2KX16, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C143-35JI CYPRESS

获取价格

 		2K x 16 Dual-Port Static RAM
CY7C143-35JIR CYPRESS

获取价格

 		Dual-Port SRAM, 2KX16, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C143-35JIT CYPRESS

获取价格

 		Dual-Port SRAM, 2KX16, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C143-55JC CYPRESS

获取价格

 		2K x 16 Dual-Port Static RAM
CY7C143-55JC ROCHESTER

获取价格

 		2KX16 DUAL-PORT SRAM, 55ns, PQCC68, PLASTIC, LCC-68
CY7C143-55JCR CYPRESS

获取价格

 		Dual-Port SRAM, 2KX16, 55ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C143-55JCT CYPRESS

获取价格

 		暂无描述
CY7C143-55JI CYPRESS

获取价格

 		2K x 16 Dual-Port Static RAM
CY7C143-55JIR CYPRESS

获取价格

 		暂无描述

与CY7C143-35JC相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证