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CY7C143-35JI PDF预览

CY7C143-35JI

更新时间： 2024-11-30 22:03:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
13页 551K
描述
2K x 16 Dual-Port Static RAM

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中文翻译

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CY7C143-35JI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：LCC包装说明：QCCJ, LDCC68,1.0SQ
针数：68Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：5.36Base Number Matches：1

CY7C143-35JI 数据手册

 浏览型号CY7C143-35JI的Datasheet PDF文件第2页浏览型号CY7C143-35JI的Datasheet PDF文件第3页浏览型号CY7C143-35JI的Datasheet PDF文件第4页浏览型号CY7C143-35JI的Datasheet PDF文件第5页浏览型号CY7C143-35JI的Datasheet PDF文件第6页浏览型号CY7C143-35JI的Datasheet PDF文件第7页 
CY7C133  
CY7C143  
2K x 16 Dual-Port Static RAM  
Features  
Functional Description  
• True dual-ported memory cells which allow  
The CY7C133 and CY7C143 are high-speed CMOS 2K by 16  
dual-port static RAMs. Two ports are provided permitting  
independent access to any location in memory. The CY7C133  
can be utilized as either a stand-alone 16-bit dual-port static  
RAM or as a master dual-port RAM in conjunction with the  
CY7C143 slave dual-port device in systems requiring 32-bit or  
greater word widths. It is the solution to applications requiring  
shared or buffered data, such as cache memory for DSP,  
bit-slice, or multiprocessor designs.  
simultaneous reads of the same memory location  
• 2K x 16 organization  
• 0.65-micron CMOS for optimum speed/power  
• High-speed access: 25/35/55 ns  
• Low operating power: ICC = 150 mA (typ.)  
• Fully asynchronous operation  
• Master CY7C133 expands data bus width to 32 bits or  
more using slave CY7C143  
• BUSY output flag on CY7C133; BUSY input flag on  
CY7C143  
• Available in 68-pin PLCC  
Each port has independent control pins; Chip Enable (CE),  
Write Enable (R/WUB, R/WLB), and Output Enable (OE).  
BUSY signals that the port is trying to access the same  
location currently being accessed by the other port. An  
automatic power-down feature is controlled independently on  
each port by the Chip Enable (CE) pin.  
The CY7C133 and CY7C143 are available in 68-pin PLCC.  
Logic Block Diagram  
CE  
R
CE  
L
R/W  
LUB  
R/W  
RUB  
R/W  
RLB  
R/W  
LLB  
OE  
R
OE  
L
I/O – I/O  
I/O – I/O  
8R  
8L  
15L  
15R  
I/O  
CONTROL  
I/O  
CONTROL  
I/O – I/O  
0L  
I/O – I/O  
0R  
7L  
7R  
]
[1  
[1]  
BUSY  
BUSY  
L
R
A
A
10L  
10R  
0R  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
MEMORY  
ARRAY  
A
0L  
A
ARBITRATION  
LOGIC  
CE  
OE  
CE  
L
L
R
OE  
R
(CY7C133 ONLY)  
R/W  
R/W  
RUB  
RLB  
LUB  
R/W  
R/W  
LLB  
Note:  
1. CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input.  
Cypress Semiconductor Corporation  
Document #: 38-06036 Rev. *B  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised June 22, 2004  
1234567...13

中文翻译

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与CY7C143-35JI相关器件

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CY7C143-55JCR CYPRESS

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CY7C143-55JCT CYPRESS

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 		暂无描述
CY7C143-55JI CYPRESS

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CY7C143-55JIR CYPRESS

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CY7C143-55JIT CYPRESS

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CY7C144 CYPRESS

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