Datasheet > CY7C144_09

CY7C144_09

更新时间： 2024-12-01 06:51:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
20页	641K
描述
8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY

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CY7C144_09 数据手册

CY7C144, CY7C145

8K x 8/9 Dual-Port Static RAM

with SEM, INT, BUSY

Features

Functional Description

■ True Dual-Ported Memory Cells that Enable Simultaneous

Reads of the same Memory Location

The CY7C144 and CY7C145 are high speed CMOS 8K x 8 and

8K x 9 dual-port static RAMs. Various arbitration schemes are

included on the CY7C144/5 to handle situations when multiple

processors access the same piece of data. Two ports are

provided permitting independent, asynchronous access for

reads and writes to any location in memory. The CY7C144/5 can

be used as a standalone 64/72-Kbit dual-port static RAM or

multiple devices can be combined in order to function as a

16/18-bit or wider master/slave dual-port static RAM. An M/S pin

is provided for implementing 16/18-bit or wider memory applica-

tions without the need for separate master and slave devices or

additional discrete logic. Application areas include interpro-

■ 8K x 8 Organization (CY7C144)

■ 8K x 9 Organization (CY7C145)

■ 0.65-Micron CMOS for optimum Speed and Power

■ High Speed Access: 15 ns

■ Low Operating Power: I_CC= 160 mA (max.)

■ Fully Asynchronous Operation

■ Automatic Power Down

cessor/multiprocessor

designs,

communications

status

buffering, and dual-port video/graphics memory.

■ TTL Compatible

Each port has independent control pins: chip enable (CE), read

or write enable (R/W), and output enable (OE). Two flags, BUSY

and INT, are provided on each port. BUSY signals that the port

is trying to access the same location currently being accessed

by the other port. The interrupt flag (INT) permits communication

between ports or systems by means of a mail box. The

semaphores are used to pass a flag, or token, from one port to

the other to indicate that a shared resource is in use. The

semaphore logic is comprised of eight shared latches. Only one

side can control the latch (semaphore) at any time. Control of a

semaphore indicates that a shared resource is in use. An

automatic power down feature is controlled independently on

each port by a chip enable (CE) pin or SEM pin.

■ Master/SlaveSelectPinenablesBusWidthExpansionto16/18

Bits or more

■ Busy Arbitration Scheme provided

■ Semaphores included to permit Software Handshaking

between Ports

■ INT Flag for Port-to-Port Communication

■ Available in 68-pin PLCC, 64-pin and 80-pin TQFP

■ Pb-free Packages available

R/W

Logic Block Diagram

(7C145) I/O

I/O (7C145)

I/O

CONTROL

I/O

CONTROL

I/O

[1, 2]

BUSY

12L

12R

MEMORY

ARRAY

ADDRESS

DECODER

ADDRESS

DECODER

INTERRUPT

SEMAPHORE

ARBITRATION

R/W

SEM

[2]

INT

INT [2]

M/S

Notes

1. BUSY is an output in master mode and an input in slave mode.

2. Interrupt: push-pull output and requires no pull-up resistor.

Cypress Semiconductor Corporation

Document #: 38-06034 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 26, 2009

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CY7C1440AV25-167BZC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV25-167BZI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV25-167BZXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV25-167BZXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV25-200AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV25-200AXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV25-200BZC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

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