Datasheet > CY7C1440AV33_12

CY7C1440AV33_12

更新时间： 2024-12-01 12:21:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
33页	809K
描述
36-Mbit (1 M Ã 36) Pipelined Sync SRAM

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中文翻译

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数据手册

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CY7C1440AV33_12 数据手册

CY7C1440AV33

36-Mbit (1 M × 36) Pipelined Sync SRAM

36-Mbit (1

M × 36) Pipelined Sync SRAM

Features

Functional Description

■ Supports bus operation up to 250 MHz

■ Available speed grades are 250 and 167 MHz

■ Registered inputs and outputs for pipelined operation

■ 3.3 V core power supply

The CY7C1440AV33 SRAM integrates 1 M × 36 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit counter

for internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered clock input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining chip enable (CE₁), depth-expansion

chip enables (CE₂and CE₃), burst control inputs (ADSC, ADSP,

and ADV), write enables (BW_Xand BWE), and global write (GW).

Asynchronous inputs include the output enable (OE) and the ZZ

pin.

■ 2.5 V/3.3 V I/O power supply

■ Fast clock-to-output times

❐ 2.6 ns (for 250-MHz device)

Addresses and chip enables are registered at rising edge of

clock when either address strobe processor (ADSP) or address

strobe controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

advance pin (ADV).

■ Provide high-performance 3-1-1-1 access rate

■ User-selectable burst counter supporting Intel^Pentium^

interleaved or linear burst sequences

■ Separate processor and controller address strobes

■ Synchronous self-timed writes

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed write cycle.This part supports byte write

operations (see pin descriptions and truth table for further

details). Write cycles can be one to two or four bytes wide as

■ Asynchronous output enable

■ Single cycle chip deselect

controlled by the byte write control inputs. GW when active

causes all bytes to be written.

LOW

■ CY7C1440AV33 available in Pb-free 100-pin TQFP package,

Pb-free 165-ball FBGA package.

The CY7C1440AV33 operates from a +3.3 V core power supply

while all outputs may operate with either a +2.5 or +3.3 V supply.

■ IEEE 1149.1 JTAG-compatible boundary scan

■ “ZZ” sleep mode option

All

inputs

and

outputs

are

JEDEC-standard

JESD8-5-compatible.

Selection Guide

Description

Maximum access time

250 MHz

2.6

167 MHz Unit

3.4

375

120

Maximum operating current

475

Maximum CMOS standby current

120

Cypress Semiconductor Corporation

Document Number: 38-05383 Rev. *K

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 14, 2012

12 3 4 5 6 7...33

中文翻译

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与CY7C1440AV33_12相关器件

型号	品牌	获取价格	描述	数据表
CY7C1440AV33-167AC	CYPRESS	获取价格	Cache SRAM, 1MX36, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1440AV33-167AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV33-167AXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV33-167BZC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV33-167BZI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV33-167BZXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV33-167BZXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV33-200AC	CYPRESS	获取价格	Cache SRAM, 1MX36, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1440AV33-200AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV33-200AXCT	CYPRESS	获取价格	Cache SRAM, 1MX36, 3.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ

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