Datasheet > CY7C1440AV25-250BZXIT

CY7C1440AV25-250BZXIT

更新时间： 2024-12-01 19:31:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
33页	611K
描述
SRAM

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C1440AV25-250BZXIT 技术参数

生命周期：	Obsolete	Reach Compliance Code：	compliant
风险等级：	5.8	Base Number Matches：	1

CY7C1440AV25-250BZXIT 数据手册

浏览型号CY7C1440AV25-250BZXIT的Datasheet PDF文件第2页

浏览型号CY7C1440AV25-250BZXIT的Datasheet PDF文件第3页

浏览型号CY7C1440AV25-250BZXIT的Datasheet PDF文件第4页

浏览型号CY7C1440AV25-250BZXIT的Datasheet PDF文件第5页

浏览型号CY7C1440AV25-250BZXIT的Datasheet PDF文件第6页

CY7C1440AV25

CY7C1446AV25

36-Mbit (1 M × 36/512 K × 72)

Pipelined Sync SRAM

36-Mbit (1

M × 36/512 K × 72) Pipelined Sync SRAM

Features

Functional Description

■ Supports bus operation up to 250 MHz

■ Available speed grades are 250 and 167 MHz

■ Registered inputs and outputs for pipelined operation

■ 2.5 V core power supply

The

CY7C1440AV25/CY7C1446AV25 SRAM

integrates

1 M × 36/512 K × 72 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE₁), depth-expansion Chip

Enables (CE₂and CE₃), Burst Control inputs (ADSC, ADSP, and

ADV), Write Enables (BW_X, and BWE), and Global Write (GW).

Asynchronous inputs include the Output Enable (OE) and the ZZ

pin.

■ 2.5 V power supply

■ Fast clock-to-output times

❐ 2.6 ns (for 250-MHz device)

■ Provide high-performance 3-1-1-1 access rate

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or Address

Strobe Controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

Advance pin (ADV).

■ User-selectable burst counter supporting Intel^ Pentium^

interleaved or linear burst sequences

■ Separate processor and controller address strobes

■ Synchronous self-timed writes

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

■ Asynchronous output enable

■ Single-cycle Chip Deselect

controlled by the byte write control inputs. GW when active

causes all bytes to be written.

LOW

■ CY7C1440AV25 available in Pb-free and non-Pb-free 165-ball

FBGA package. CY7C1446AV25 available in non-Pb-free

209-ball FBGA package

The CY7C1440AV25/CY7C1446AV25 operates from a +2.5 V

core power supply while all outputs may operate with a +2.5 V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

■ IEEE 1149.1 JTAG-Compatible Boundary Scan

■ “ZZ” Sleep Mode Option

For a complete list of related documentation, click here.

Selection Guide

Description

Maximum Access Time

250 MHz

2.6

167 MHz Unit

3.4

335

120

Maximum Operating Current

435

Maximum CMOS Standby Current

120

Cypress Semiconductor Corporation

Document Number: 001-70167 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 5, 2016

12 3 4 5 6 7...33

中文翻译

下载PDF

与CY7C1440AV25-250BZXIT相关器件

型号	品牌	获取价格	描述	数据表
CY7C1440AV33	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV33_06	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV33_12	CYPRESS	获取价格	36-Mbit (1 M Ã 36) Pipelined Sync SRAM
CY7C1440AV33-167AC	CYPRESS	获取价格	Cache SRAM, 1MX36, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1440AV33-167AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV33-167AXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV33-167BZC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV33-167BZI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV33-167BZXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1440AV33-167BZXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

与CY7C1440AV25-250BZXIT相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

53
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

42
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

70
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

66

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1440AV25-250BZXIT

CY7C1440AV25-250BZXIT 技术参数

CY7C1440AV25-250BZXIT 数据手册

与CY7C1440AV25-250BZXIT相关器件

与CY7C1440AV25-250BZXIT相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1440AV25-250BZXIT

CY7C1440AV25-250BZXIT 技术参数

CY7C1440AV25-250BZXIT 数据手册

与CY7C1440AV25-250BZXIT相关器件

与CY7C1440AV25-250BZXIT相关文章

您还可以找

您在本页遇到什么问题？