Datasheet > CY7C1362C-166BGCT

CY7C1362C-166BGCT

更新时间： 2024-11-16 19:50:47

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		静态存储器内存集成电路
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31页	571K
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CY7C1360C

CY7C1362C

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Features

Functional Description^[1]

• Supports bus operation up to 250 MHz

The CY7C1360C/CY7C1362C SRAM integrates 256K x 36

and 512K x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE₁), depth-expansion Chip

Enables (CE₂and CE₃^[2]), Burst Control inputs (ADSC, ADSP,

• Available speed grades are 250, 200, and 166 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply (V_DD

)

• 2.5V/3.3V I/O operation (V_DDQ

)

• Fast clock-to-output times

ADV), Write Enables (BW , and BWE), and Global Write

(GW). Asynchronous inputs include the Output Enable (OE)

and the ZZ pin.

and

— 2.8 ns (for 250-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the Byte Write control inputs. GW when active

• Single Cycle Chip Deselect

• Available in lead-free 100-Pin TQFP package, lead-free

and non lead-free 119-Ball BGA package and 165-Ball

FBGA package

LOW cause

s all bytes to be written.

• TQFP Available with 3-Chip Enable and 2-Chip Enable

• IEEE 1149.1 JTAG-Compatible Boundary Scan

The CY7C1360C/CY7C1362C operates from a +3.3V core

power supply while all outputs may operate with either a +2.5

or +3.3V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Logic Block Diagram – CY7C1362C (512K x 18)

ADDRESS

A0, A1, A

A[1:0]

MODE

ADV

CLK

BURST

COUNTER AND

LOGIC

CLR

ADSC

ADSP

DQB,DQP

WRITE REGISTER

WRITE DRIVER

OUTPUT

BUFFERS

DQs

DQP

OUTPUT

REGISTERS

SENSE

AMPS

MEMORY

ARRAY

DQA,DQP

WRITE REGISTER

WRITE DRIVER

BWE

INPUT

REGISTERS

ENABLE

CE1

CE2

PIPELINED

ENABLE

CE3

SLEEP

CONTROL

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE is for A version of TQFP (3 Chip Enable option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.

Cypress Semiconductor Corporation

Document #: 38-05540 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 14, 2006

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与CY7C1362C-166BGCT相关器件

型号	品牌	获取价格	描述	数据表
CY7C1362C-166BGI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362C-166BGXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362C-166BGXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362C-166BZC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362C-166BZCT	ROCHESTER	获取价格	Cache SRAM, 512KX18, 3.5ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CY7C1362C-166BZI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362C-166BZXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362C-166BZXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362C-200AJXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362C-200AJXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined SRAM

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