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CY7C1362C-200AXCT PDF预览

CY7C1362C-200AXCT

更新时间： 2024-11-16 19:53:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
34页 804K
描述
QDR SRAM, 512KX18, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100

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CY7C1362C-200AXCT 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.29
最长访问时间：3 ns其他特性：PIPELINED ARCHITECTURE
JESD-30 代码：R-PQFP-G100JESD-609代码：e3/e4
长度：20 mm内存密度：9437184 bit
内存集成电路类型：QDR SRAM内存宽度：18
功能数量：1端子数量：100
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：512KX18
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：MATTE TIN/NICKEL PALLADIUM GOLD
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

CY7C1362C-200AXCT 数据手册

 浏览型号CY7C1362C-200AXCT的Datasheet PDF文件第2页浏览型号CY7C1362C-200AXCT的Datasheet PDF文件第3页浏览型号CY7C1362C-200AXCT的Datasheet PDF文件第4页浏览型号CY7C1362C-200AXCT的Datasheet PDF文件第5页浏览型号CY7C1362C-200AXCT的Datasheet PDF文件第6页浏览型号CY7C1362C-200AXCT的Datasheet PDF文件第7页 
CY7C1360C, CY7C1362C  
9-Mbit (256 K × 36/512 K × 18)  
Pipelined SRAM  
9-Mbit (256  
K × 36/512 K × 18) Pipelined SRAM  
Features  
Functional Description  
n Supports bus operation up to 250 MHz  
The CY7C1360C/CY7C1362C SRAM[1] integrates 256 K × 36  
and 512 K × 18 SRAM cells with advanced synchronous  
peripheral circuitry and a two-bit counter for internal burst  
operation. All synchronous inputs are gated by registers  
controlled by a positive-edge-triggered clock input (CLK). The  
synchronous inputs include all addresses, all data inputs,  
address-pipelining chip enable (CE1), depth-expansion chip  
enables (CE2 and CE3[2]), burst control inputs (ADSC, ADSP,  
n Available speed grades: 250, 200, and 166 MHz  
n Registered inputs and outputs for pipelined operation  
n 3.3 V core power supply (VDD  
)
n 2.5 V/3.3 V I/O operation (VDDQ  
)
n Fast clock-to-output times  
p 2.8 ns (for 250 MHz device)  
ADV), write enables (BWX, and BWE), and global write  
(GW). Asynchronous inputs include the output enable (OE) and  
the ZZ pin.  
and  
n Provide high performance 3-1-1-1 access rate  
Addresses and chip enables are registered at the rising edge of  
clock when either address strobe processor (ADSP) or address  
strobe controller (ADSC) are active. Subsequent burst  
addresses can be internally generated as controlled by the  
advance pin (ADV).  
n User selectable burst counter supporting Intel® Pentium®  
interleaved or linear burst sequences  
n Separate processor and controller address strobes  
n Synchronous self-timed writes  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed write cycle.This part supports byte write  
operations (see “Pin Definitions” on page 8 and “Truth Table” on  
page 11 for further details). Write cycles can be one to two or four  
bytes wide as controlled by the byte write control inputs. GW  
n Asynchronous output enable  
n Single cycle chip deselect  
n Available in Pb-free 100-pin TQFP package, Pb-free and non  
Pb-free 119-ball BGA package, and 165-ball FBGA package  
when active LOW cause  
s all bytes to be written.  
The CY7C1360C/CY7C1362C operate from a +3.3 V core power  
supply while all outputs may operate with either a +2.5 or +3.3 V  
supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
n TQFP available with 3-chip enable and 2-chip enable  
n IEEE 1149.1 JTAG-compatible boundary scan  
Logic Block Diagram – CY7C1362C (512 K × 18)  
ADDRESS  
REGISTER  
A0, A1,  
A
A[1:0]  
2
MODE  
Q1  
ADV  
CLK  
BURST  
COUNTER AND  
LOGIC  
CLR  
Q0  
ADSC  
ADSP  
DQ B, DQP B  
WRITE DRIVER  
DQ B, DQP B  
WRITE REGISTER  
OUTPUT  
DQs  
BW  
B
OUTPUT  
REGISTERS  
SENSE  
AMPS  
MEMORY  
ARRAY  
BUFFERS  
DQP  
DQP  
A
B
DQ A, DQP A  
WRITE DRIVER  
E
DQ A, DQP A  
WRITE REGISTER  
BW  
A
BWE  
GW  
INPUT  
REGISTERS  
ENABLE  
REGISTER  
CE1  
CE2  
PIPELINED  
ENABLE  
CE3  
OE  
SLEEP  
CONTROL  
ZZ  
Notes  
1. For best-practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. CE is for A version of TQFP (3 Chip Enable option) and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable.  
3
Cypress Semiconductor Corporation  
Document Number: 38-05540 Rev. *K  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised October 11, 2010  
[+] Feedback  
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CY7C1362C-200AXCT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1362C-200AXC CYPRESS

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