Datasheet > CY7C136-30JCT

CY7C136-30JCT

更新时间： 2024-11-17 09:39:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
15页	462K
描述
Dual-Port SRAM, 2KX8, 30ns, CMOS, PQCC52, PLASTIC, LCC-52

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CY7C136-30JCT 数据手册

CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

2K x 8 Dual-Port Static RAM

Features

Functional Description

■ True dual-ported memory cells that enable simultaneous reads

of the same memory location

The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146

are high speed CMOS 2K x 8 dual-port static RAMs. Two ports

are provided to permit independent access to any location in

memory. The CY7C132, CY7C136, and CY7C136A can be used

as either a standalone 8-bit dual-port static RAM or as a

MASTER dual-port RAM, in conjunction with the

CY7C142/CY7C146 SLAVE dual-port device. They are used in

systems that require 16-bit or greater word widths. This is the

solution to applications that require shared or buffered data, such

as cache memory for DSP, bit-slice, or multiprocessor designs.

■ 2K x 8 organization

■ 0.65 micron CMOS for optimum speed and power

■ High speed access: 15 ns

■ Low operating power: I_CC= 110 mA (maximum)

■ Fully asynchronous operation

■ Automatic power down

Each port has independent control pins; chip enable (CE), write

enable (R/W), and output enable (OE). BUSY flags are provided

on each port. In addition, an interrupt flag (INT) is provided on

each port of the 52-pin PLCC version. BUSY signals that the port

is trying to access the same location currently being accessed

by the other port. On the PLCC version, INT is an interrupt flag

indicating that data is placed in an unique location (7FF for the

left port and 7FE for the right port).

■ MasterCY7C132/CY7C136/CY7C136A^[1]easilyexpandsdata

bus width to 16 or more bits using slave CY7C142/CY7C146

■ BUSY output flag on CY7C132/CY7C136/CY7C136A;

BUSY input on CY7C142/CY7C146

■ INT flag for port to port communication (52-Pin PLCC/PQFP

versions)

An automatic power down feature is controlled independently on

each port by the chip enable (CE) pins.

■ CY7C136, CY7C136A, and CY7C146 available in 52-pin

PLCC and 52-pin PQFP packages

■ Pb-free packages available

Logic Block Diagram

R/W

I/O

CONTROL

I/O

CONTROL

[2]

BUSY

10L

10R

MEMORY

ARRAY

ADDRESS

DECODER

ADDRESS

DECODER

ARBITRATION

LOGIC

(7C132/7C136 ONLY)

AND

INTERRUPTLOGIC

(7C136/7C146ONLY)

R/W

[3]

INT

Notes

1. CY7C136 and CY7C136A are functionally identical.

2. CY7C132/CY7C136/CY7C136A (Master): BUSY is open drain output and requires pull up resistor. CY7C142/CY7C146 (Slave): BUSY is input.

3. Open drain outputs; pull up resistor required.

Cypress Semiconductor Corporation

Document #: 38-06031 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 24, 2009

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中文翻译

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与CY7C136-30JCT相关器件

型号	品牌	获取价格	描述	数据表
CY7C136-30JI	CYPRESS	获取价格	2Kx8 Dual-Port Static RAM
CY7C136-30LC	ETC	获取价格	x8 Dual-Port SRAM
CY7C136-30NC	CYPRESS	获取价格	2Kx8 Dual-Port Static RAM
CY7C136-30NCT	CYPRESS	获取价格	Dual-Port SRAM, 2KX8, 30ns, CMOS, PQFP52, PLASTIC, QFP-52
CY7C136-35JC	CYPRESS	获取价格	2Kx8 Dual-Port Static RAM
CY7C136-35JCT	CYPRESS	获取价格	Dual-Port SRAM, 2KX8, 35ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C136-35JI	CYPRESS	获取价格	2Kx8 Dual-Port Static RAM
CY7C136-35JIR	CYPRESS	获取价格	暂无描述
CY7C136-35JIT	CYPRESS	获取价格	暂无描述
CY7C136-35JXCT	CYPRESS	获取价格	Dual-Port SRAM, 2KX8, 35ns, CMOS, PQCC52, LEAD FREE, PLASTIC, LCC-52

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