Datasheet > CY7C1354V25-133BGC

CY7C1354V25-133BGC

更新时间： 2024-11-18 15:30:15

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		静态存储器内存集成电路
页数	文件大小	规格书
27页	702K
描述
ZBT SRAM, 256KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

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CY7C1354V25-133BGC 技术参数

生命周期：	Contact Manufacturer	包装说明：	BGA,
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.71
最长访问时间：	4.2 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PBGA-B119	长度：	22 mm
内存密度：	9437184 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	36	功能数量：	1
端子数量：	119	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX36	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
座面最大高度：	2.4 mm	最大供电电压 (Vsup)：	2.625 V
最小供电电压 (Vsup)：	2.375 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
宽度：	14 mm	Base Number Matches：	1

CY7C1354V25-133BGC 数据手册

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356V25

CY7C1354V25

CY7C1356V25

PRELIMINARY

256Kx36/512Kx18 Pipelined SRAM with NoBL™ Architecture

spectively. They are designed specifically to support unlimited

Features

true back-to-back Read/Write operations without the insertion

of wait states. The CY7C1354V25/CY7C1356V25 is equipped

with the advanced No Bus Latency™ (NoBL™) logic required

to enable consecutive Read/Write operations with data being

transferred on every clock cycle. This feature dramatically im-

proves the throughput of data through the SRAM, especially in

systems that require frequent Write/Read transitions. The

CY7C1354V25/CY7C1356V25 is pin compatible and function-

ally equivalent to ZBT devices.

• Pin compatible and functionally equivalent to ZBT™

• Supports 200-MHz bus operations with zero wait states

— Data is transferred on every clock

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

• Fully Registered (inputs and outputs) for pipelined op-

eration

• Byte Write capability

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal, which

when deasserted suspends operation and extends the previ-

ous clock cycle. Maximum access delay from the clock rise is

3.2 ns (200-MHz device).

• Common I/O architecture

• Single 2.5V power supply

• Fast clock-to-output times

— 3.2 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

— 4.2 ns (for 133-MHz device)

Write operations are controlled by the Byte Write Selects

(BWS_a–BWS_dfor CY7C1354V25 and BWS_a–BWS_bfor

CY7C1356V25) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

— 5.0 ns (for 100-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Available in 100 TQFP & 119 BGA Packages

• Burst Capability—linear or interleaved burst order

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Functional Description

The CY7C1354V25 and CY7C1356V25 are 2.5V, 256K by 36

and 512K by 18 Synchronous-Pipelined Burst SRAMs, re-

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

CEN

CONTROL

and WRITE

LOGIC

256KX36/

512KX18

MEMORY

ARRAY

CY7C1354 CY7C1356

X = 17:0 X = 18:0

BWS

Mode

X = a, b, c, d X = a, b

BWS

Selection Guide

7C1354V25-200 7C1354V25-166 7C1354V25-133 7C1354V25-100

7C1356V25-200 7C1356V25-166 7C1356V25-133 7C1356V25-100

Maximum Access Time (ns)

3.2

475

3.5

450

4.0

370

5.0

300

Maximum Operating Current (mA)

Com’l

Maximum CMOS Standby Current (mA) Com’l

Shaded areas contain advance information.

No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.

ZBT is a trademark of Integrated Device Technology.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05263 Rev. **

Revised March 6, 2002

12 3 4 5 6 7...27

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与CY7C1354V25-133BGC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1354V25-166AC	CYPRESS	获取价格	ZBT SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1354V25-166BAC	CYPRESS	获取价格	ZBT SRAM, 256KX36, 3.5ns, CMOS, PBGA119, BGA-119
CY7C1354V25-200BAC	CYPRESS	获取价格	ZBT SRAM, 256KX36, 3.2ns, CMOS, PBGA119, BGA-119
CY7C1354V25-200BGC	CYPRESS	获取价格	暂无描述
CY7C135-55JC	CYPRESS	获取价格	4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
CY7C135-55JCT	CYPRESS	获取价格	Dual-Port SRAM, 4KX8, 55ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C135-55JI	CYPRESS	获取价格	4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
CY7C135-55JIR	CYPRESS	获取价格	Dual-Port SRAM, 4KX8, 55ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C135-55JIT	CYPRESS	获取价格	Dual-Port SRAM, 4KX8, 55ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C1355A	CYPRESS	获取价格	256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture

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