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CY7C1355A-133BGC PDF预览

CY7C1355A-133BGC

更新时间： 2024-11-18 15:30:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
31页 573K
描述
ZBT SRAM, 256KX36, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119

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CY7C1355A-133BGC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
针数：119Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.84最长访问时间：6.5 ns
其他特性：FLOW-THROUGH ARCHITECTURE最大时钟频率 (fCLK)：133 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：9437184 bit内存集成电路类型：ZBT SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：119
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA119,7X17,50
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：220
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：2.4 mm最大待机电流：0.03 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.41 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

CY7C1355A-133BGC 数据手册

 浏览型号CY7C1355A-133BGC的Datasheet PDF文件第2页浏览型号CY7C1355A-133BGC的Datasheet PDF文件第3页浏览型号CY7C1355A-133BGC的Datasheet PDF文件第4页浏览型号CY7C1355A-133BGC的Datasheet PDF文件第5页浏览型号CY7C1355A-133BGC的Datasheet PDF文件第6页浏览型号CY7C1355A-133BGC的Datasheet PDF文件第7页 
CY7C1357A  
CY7C1355A  
256K x 36/512K x 18 Synchronous Flow-Thru  
SRAM with NoBL™ Architecture  
inputs include all addresses, all data inputs, depth-expansion  
Chip Enables (CE, CE2, and CE3), Cycle Start Input (ADV/LD),  
Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc,  
and BWd), and read-write control (WEN). BWc and BWd apply  
to CY7C1355A/GVT71256ZB36 only.  
Features  
• Zero Bus Latency, no dead cycles between write and  
read cycles  
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns  
• Fast clock speed: 133, 117, and 100 MHz  
• Fast OE access time: 6.5, 7.0, 7.5, and 8.0 ns  
• Internally synchronized registered outputs eliminate  
the need to control OE  
Address and control signals are applied to the SRAM during  
one clock cycle, and one cycle later, its associated data  
occurs, either read or write.  
A
Clock Enable (CEN) pin allows operation of the  
CY7C1355A/CY7C1357A/GVT71256ZB36/GVT71512ZB18  
to be suspended as long as necessary. All synchronous inputs  
are ignored when (CEN) is HIGH and the internal device  
registers will hold their previous values.  
• 3.3V –5% and +5% power supply  
• 3.3V or 2.5V I/O supply  
• Single WEN (READ/WRITE) control pin  
• Positive clock-edge triggered, address, data, and  
control signal registers for fully pipelined applications  
• Interleaved or linear four-word burst capability  
• Individual byte write (BWa–BWd) control (may be tied  
LOW)  
• CEN pin to enable clock and suspend operations  
• Three chip enables for simple depth expansion  
• Automatic Power-down fearture available using ZZ  
mode or CE deselect.  
There are three Chip Enable pins (CE, CE2, CE3) that allow  
the user to deselect the device when desired. If any one of  
these three are not active when ADV/LD is LOW, no new  
memory operation can be initiated and any burst cycle in  
progress is stopped. However, any pending data transfers  
(read or write) will be completed. The data bus will be in  
high-impedance state one cycle after chip is deselected or a  
write cycle is initiated.  
The  
CY7C1355A/GVT71256ZB36  
and  
CY7C1357A/  
GVT71512ZB18 have an on-chip 2-bit burst counter. In the  
burst mode, the CY7C1355A/GVT71256ZB36 and  
CY7C1357A/GVT71512ZB18 provide four cycles of data for a  
single address presented to the SRAM. The order of the burst  
sequence is defined by the MODE input pin. The MODE pin  
selects between linear and interleaved burst sequence. The  
ADV/LD signal is used to load a new external address  
(ADV/LD = LOW) or increment the internal burst counter  
(ADV/LD = HIGH)  
• JTAG boundary scan  
• Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid  
Array) and 100-pin TQFP packages  
Functional Description  
The  
CY7C1355A/GVT71256ZB36  
and  
CY7C1357A/  
GVT71512ZB18 SRAMs are designed to eliminate dead  
cycles when transitions from READ to WRITE or vice versa.  
These SRAMs are optimized for 100 percent bus utilization  
and achieves Zero Bus Latency (ZBL). They integrate 262,144  
× 36 and 524,288 × 18 SRAM cells, respectively, with  
advanced synchronous peripheral circuitry and a 2-bit counter  
for internal burst operation. These employ high-speed, low  
power CMOS designs using advanced triple-layer polysilicon,  
double-layer metal technology. Each memory cell consists of  
Six transistors.  
Output Enable (OE), Sleep Enable (ZZ) and burst sequence  
select (MODE) are the asynchronous signals. OE can be used  
to disable the outputs at any given time. ZZ may be tied to  
LOW if it is not used.  
Four pins are used to implement JTAG test capabilities. The  
JTAG circuitry is used to serially shift data to and from the  
device. JTAG inputs use LVTTL/LVCMOS levels to shift data  
during this testing mode of operation.  
All synchronous inputs are gated by registers controlled by a  
positive-edge-triggered Clock Input (CLK). The synchronous  
Selection Guide  
7C1355A-133  
71256ZB36-6.5  
7C1357A-133  
71512ZB18-6.5  
7C1355A-117  
71256ZB36-7  
7C1357A-117  
71512ZB18-7  
7C1355A-100  
71256ZB36-7.5  
7C1357A-100  
71512ZB18-7.5  
7C1355A1-100  
71256ZB36-8  
7C1357A1-100  
71512ZB18-8  
Unit  
ns  
Maximum Access Time  
6.5  
410  
30  
7
7.5  
350  
30  
8
Maximum Operating Current  
Maximum CMOS Standby Current  
385  
30  
350  
30  
mA  
mA  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05265 Rev. **  
Revised July 11, 2002  
1234567...31

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