Datasheet > CY7C1355A1-100BGI

CY7C1355A1-100BGI

更新时间： 2024-11-19 05:09:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	573K
描述
ZBT SRAM, 256KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119

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CY7C1357A

CY7C1355A

256K x 36/512K x 18 Synchronous Flow-Thru

SRAM with NoBL™ Architecture

inputs include all addresses, all data inputs, depth-expansion

Chip Enables (CE, CE₂, and CE₃), Cycle Start Input (ADV/LD),

Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc,

and BWd), and read-write control (WEN). BWc and BWd apply

to CY7C1355A/GVT71256ZB36 only.

Features

• Zero Bus Latency, no dead cycles between write and

read cycles

• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns

• Fast clock speed: 133, 117, and 100 MHz

• Fast OE access time: 6.5, 7.0, 7.5, and 8.0 ns

• Internally synchronized registered outputs eliminate

the need to control OE

Address and control signals are applied to the SRAM during

one clock cycle, and one cycle later, its associated data

occurs, either read or write.

Clock Enable (CEN) pin allows operation of the

CY7C1355A/CY7C1357A/GVT71256ZB36/GVT71512ZB18

to be suspended as long as necessary. All synchronous inputs

are ignored when (CEN) is HIGH and the internal device

registers will hold their previous values.

• 3.3V –5% and +5% power supply

• 3.3V or 2.5V I/O supply

• Single WEN (READ/WRITE) control pin

• Positive clock-edge triggered, address, data, and

control signal registers for fully pipelined applications

• Interleaved or linear four-word burst capability

• Individual byte write (BWa–BWd) control (may be tied

LOW)

• CEN pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• Automatic Power-down fearture available using ZZ

mode or CE deselect.

There are three Chip Enable pins (CE, CE₂, CE₃) that allow

the user to deselect the device when desired. If any one of

these three are not active when ADV/LD is LOW, no new

memory operation can be initiated and any burst cycle in

progress is stopped. However, any pending data transfers

(read or write) will be completed. The data bus will be in

high-impedance state one cycle after chip is deselected or a

write cycle is initiated.

The

CY7C1355A/GVT71256ZB36

and

CY7C1357A/

GVT71512ZB18 have an on-chip 2-bit burst counter. In the

burst mode, the CY7C1355A/GVT71256ZB36 and

CY7C1357A/GVT71512ZB18 provide four cycles of data for a

single address presented to the SRAM. The order of the burst

sequence is defined by the MODE input pin. The MODE pin

selects between linear and interleaved burst sequence. The

ADV/LD signal is used to load a new external address

(ADV/LD = LOW) or increment the internal burst counter

(ADV/LD = HIGH)

• JTAG boundary scan

• Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid

Array) and 100-pin TQFP packages

Functional Description

The

CY7C1355A/GVT71256ZB36

and

CY7C1357A/

GVT71512ZB18 SRAMs are designed to eliminate dead

cycles when transitions from READ to WRITE or vice versa.

These SRAMs are optimized for 100 percent bus utilization

and achieves Zero Bus Latency (ZBL). They integrate 262,144

× 36 and 524,288 × 18 SRAM cells, respectively, with

advanced synchronous peripheral circuitry and a 2-bit counter

for internal burst operation. These employ high-speed, low

power CMOS designs using advanced triple-layer polysilicon,

double-layer metal technology. Each memory cell consists of

Six transistors.

Output Enable (OE), Sleep Enable (ZZ) and burst sequence

select (MODE) are the asynchronous signals. OE can be used

to disable the outputs at any given time. ZZ may be tied to

LOW if it is not used.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

Selection Guide

7C1355A-133

71256ZB36-6.5

7C1357A-133

71512ZB18-6.5

7C1355A-117

71256ZB36-7

7C1357A-117

71512ZB18-7

7C1355A-100

71256ZB36-7.5

7C1357A-100

71512ZB18-7.5

7C1355A1-100

71256ZB36-8

7C1357A1-100

71512ZB18-8

Unit

Maximum Access Time

6.5

410

7.5

350

Maximum Operating Current

Maximum CMOS Standby Current

385

350

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05265 Rev. **

Revised July 11, 2002

12 3 4 5 6 7...31

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与CY7C1355A1-100BGI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1355A-117AC	CYPRESS	获取价格	256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture
CY7C1355A-117AI	CYPRESS	获取价格	256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture
CY7C1355A-117BGC	CYPRESS	获取价格	256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture
CY7C1355A-117BGI	CYPRESS	获取价格	256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture
CY7C1355A-133AC	CYPRESS	获取价格	256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture
CY7C1355A-133AC	ROCHESTER	获取价格	256KX36 ZBT SRAM, 6.5ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1355A-133BGC	CYPRESS	获取价格	ZBT SRAM, 256KX36, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
CY7C1355B	CYPRESS	获取价格	9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355B-100AC	CYPRESS	获取价格	9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355B-100AI	CYPRESS	获取价格	9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

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