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CY7C1354V25-166AC

更新时间： 2024-11-18 15:30:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
27页 722K
描述
ZBT SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1354V25-166AC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：100Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.27最长访问时间：3.5 ns
其他特性：PIPELINED ARCHITECTUREI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：9437184 bit
内存集成电路类型：ZBT SRAM内存宽度：36
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL电源：2.5 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.01 A最小待机电流：2.38 V
子类别：SRAMs最大压摆率：0.45 mA
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：14 mmBase Number Matches：1

CY7C1354V25-166AC 数据手册

 浏览型号CY7C1354V25-166AC的Datasheet PDF文件第2页浏览型号CY7C1354V25-166AC的Datasheet PDF文件第3页浏览型号CY7C1354V25-166AC的Datasheet PDF文件第4页浏览型号CY7C1354V25-166AC的Datasheet PDF文件第5页浏览型号CY7C1354V25-166AC的Datasheet PDF文件第6页浏览型号CY7C1354V25-166AC的Datasheet PDF文件第7页 
356V25  
CY7C1354V25  
CY7C1356V25  
PRELIMINARY  
256Kx36/512Kx18 Pipelined SRAM with NoBL™ Architecture  
spectively. They are designed specifically to support unlimited  
Features  
true back-to-back Read/Write operations without the insertion  
of wait states. The CY7C1354V25/CY7C1356V25 is equipped  
with the advanced No Bus Latency™ (NoBL™) logic required  
to enable consecutive Read/Write operations with data being  
transferred on every clock cycle. This feature dramatically im-  
proves the throughput of data through the SRAM, especially in  
systems that require frequent Write/Read transitions. The  
CY7C1354V25/CY7C1356V25 is pin compatible and function-  
ally equivalent to ZBT devices.  
• Pin compatible and functionally equivalent to ZBT™  
• Supports 200-MHz bus operations with zero wait states  
— Data is transferred on every clock  
• Internally self-timed output buffer control to eliminate  
the need to use asynchronous OE  
• Fully Registered (inputs and outputs) for pipelined op-  
eration  
• Byte Write capability  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal, which  
when deasserted suspends operation and extends the previ-  
ous clock cycle. Maximum access delay from the clock rise is  
3.2 ns (200-MHz device).  
• Common I/O architecture  
• Single 2.5V power supply  
• Fast clock-to-output times  
— 3.2 ns (for 200-MHz device)  
— 3.5 ns (for 166-MHz device)  
— 4.2 ns (for 133-MHz device)  
Write operations are controlled by the Byte Write Selects  
(BWSa–BWSd for CY7C1354V25 and BWSa–BWSb for  
CY7C1356V25) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
— 5.0 ns (for 100-MHz device)  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
• Available in 100 TQFP & 119 BGA Packages  
• Burst Capability—linear or interleaved burst order  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank se-  
lection and output three-state control. In order to avoid bus  
contention, the output drivers are synchronously three-stated  
during the data portion of a write sequence.  
Functional Description  
The CY7C1354V25 and CY7C1356V25 are 2.5V, 256K by 36  
and 512K by 18 Synchronous-Pipelined Burst SRAMs, re-  
Logic Block Diagram  
D
CLK  
Data-In REG.  
CE  
Q
ADV/LD  
A
x
CEN  
CE  
CONTROL  
and WRITE  
LOGIC  
256KX36/  
512KX18  
MEMORY  
ARRAY  
1
CE  
CE  
2
DQ  
x
3
WE  
DP  
x
CY7C1354 CY7C1356  
X = 17:0 X = 18:0  
BWS  
x
A
X
Mode  
X = a, b, c, d X = a, b  
DQ  
X
X = a, b, c, d X = a, b  
X = a, b, c, d X = a, b  
DP  
X
BWS  
X
OE  
.
Selection Guide  
7C1354V25-200 7C1354V25-166 7C1354V25-133 7C1354V25-100  
7C1356V25-200 7C1356V25-166 7C1356V25-133 7C1356V25-100  
Maximum Access Time (ns)  
3.2  
475  
10  
3.5  
450  
10  
4.0  
370  
10  
5.0  
300  
10  
Maximum Operating Current (mA)  
Com’l  
Maximum CMOS Standby Current (mA) Com’l  
Shaded areas contain advance information.  
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.  
ZBT is a trademark of Integrated Device Technology.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05263 Rev. **  
Revised March 6, 2002  
1234567...27

中文翻译

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CY7C1354V25-166AC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1354CV25-200AXC CYPRESS

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 9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
K7N803645B-QC16 SAMSUNG

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 256Kx36 & 512Kx18-Bit Pipelined NtRAM

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CY7C1354V25-166BAC CYPRESS

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CY7C1354V25-200BAC CYPRESS

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 		ZBT SRAM, 256KX36, 3.2ns, CMOS, PBGA119, BGA-119
CY7C1354V25-200BGC CYPRESS

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CY7C135-55JC CYPRESS

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 		4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
CY7C135-55JCT CYPRESS

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 		Dual-Port SRAM, 4KX8, 55ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C135-55JI CYPRESS

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 		4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
CY7C135-55JIR CYPRESS

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 		Dual-Port SRAM, 4KX8, 55ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C135-55JIT CYPRESS

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 		Dual-Port SRAM, 4KX8, 55ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C1355A CYPRESS

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 		256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture
CY7C1355A-100AC CYPRESS

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