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Datasheet > CY7C1354V25-100BAC
CY7C1354V25-100BAC PDF预览

CY7C1354V25-100BAC

更新时间： 2024-11-18 19:31:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
25页 269K
描述
ZBT SRAM, 256KX36, 5ns, CMOS, PBGA119, BGA-119

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中文翻译

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CY7C1354V25-100BAC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：BGA-119针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.78
最长访问时间：5 nsI/O 类型：COMMON
JESD-30 代码：R-PBGA-B119JESD-609代码：e0
内存密度：9437184 bit内存集成电路类型：ZBT SRAM
内存宽度：36功能数量：1
端子数量：119字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119(UNSPEC)封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：240电源：2.5 V
认证状态：Not Qualified最大待机电流：0.01 A
最小待机电流：2.38 V子类别：SRAMs
最大压摆率：0.3 mA最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子位置：BOTTOM
处于峰值回流温度下的最长时间：30Base Number Matches：1

CY7C1354V25-100BAC 数据手册

 浏览型号CY7C1354V25-100BAC的Datasheet PDF文件第2页浏览型号CY7C1354V25-100BAC的Datasheet PDF文件第3页浏览型号CY7C1354V25-100BAC的Datasheet PDF文件第4页浏览型号CY7C1354V25-100BAC的Datasheet PDF文件第5页浏览型号CY7C1354V25-100BAC的Datasheet PDF文件第6页浏览型号CY7C1354V25-100BAC的Datasheet PDF文件第7页 
5
CY7C1354V25  
CY7C1356V25  
PRELIMINARY  
256Kx36/512Kx18 Pipelined SRAM with NoBL™ Architecture  
tively designed specifically to support unlimited true  
Features  
back-to-back Read/Write operations without the insertion of  
wait states. The CY7C1354V25/CY7C1356V25 is equipped  
with the advanced No Bus Latency™ (NoBL ) logic required  
to enable consecutive Read/Write operations with data being  
transferred on every clock cycle. This feature dramatically im-  
proves the throughput of data through the SRAM, especially in  
systems that require frequent Write/Read transitions.The  
CY7C1354V25/CY7C1356V25 is pin compatible and function-  
ally equivalent to ZBT devices.  
Pin compatible and functionally equivalent to ZBT  
• Supports 200-MHz bus operations with zero wait states  
— Data is transferred on every clock  
•
• Internally self-timed output buffer control to eliminate  
the need to use asynchronous OE  
• Fully Registered (inputs and outputs) for pipelined op-  
eration  
• Byte Write capability  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock.All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal, which  
when deasserted suspends operation and extends the previ-  
ous clock cycle. Maximum access delay from the clock rise is  
3.2 ns (200-MHz device).  
• Common I/O architecture  
• Single 2.5V power supply  
• Fast clock-to-output times  
— 3.2 ns (for 200-MHz device)  
— 3.5 ns (for 166-MHz device)  
— 4.2 ns (for 133-MHz device)  
Write operations are controlled by the Byte Write Selects  
(BWSa-BWSd for CY7C1354V25 and BWSa-BWSb for  
CY7C1356V25) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
— 5.0 ns (for 100-MHz device)  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
• Available in 100 TQFP & 119 BGA Packages  
• Burst Capability—linear or interleaved burst order  
Three synchronous Chip Enables (CE , CE , CE ) and an  
1
2
3
asynchronous Output Enable (OE) provide for easy bank se-  
lection and output three-state control. In order to avoid bus  
contention, the output drivers are synchronously three-stated  
during the data portion of a write sequence.  
Functional Description  
The CY7C1354V25 and CY7C1356V25 are 2.5V, 256K by 36  
and 512K by 18 Synchronous-Pipelined Burst SRAMs respec-  
Logic Block Diagram  
D
CLK  
Data-In REG.  
CE  
Q
ADV/LD  
Ax  
CEN  
CE  
CONTROL  
and WRITE  
LOGIC  
256KX36/  
512KX18  
MEMORY  
ARRAY  
1
CE  
2
DQx  
DPx  
CE  
3
WE  
CY7C1356  
CY7C1354  
BWSx  
X = 17:0  
AX  
X = 18:0  
Mode  
OE  
DQX X = a, b, c, d X = a, b  
X = a, b, c, d  
X = a, b  
DPX  
X = a, b, c, d X = a, b  
BWSX  
.
Selection Guide  
7C1354V25-200 7C1354V25-166 7C1354V25-133 7C1354V25-100  
7C1356V25-200 7C1356V25-166 7C1356V25-133 7C1356V25-100  
Maximum Access Time (ns)  
3.2  
475  
10  
3.5  
450  
10  
4.0  
370  
10  
5.0  
300  
10  
Maximum Operating Current (mA)  
Com’l  
Maximum CMOS Standby Current (mA) Com’l  
Shaded areas contain advance information.  
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.  
ZBT is a trademark of Integrated Device Technology.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
August 5, 1999  
1234567...25

中文翻译

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与CY7C1354V25-100BAC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1354V25-133AC ROCHESTER

获取价格

 		ZBT SRAM, 256KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1354V25-133AC CYPRESS

获取价格

 		ZBT SRAM, 256KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1354V25-133BAC CYPRESS

获取价格

 		ZBT SRAM, 256KX36, 4.2ns, CMOS, PBGA119, BGA-119
CY7C1354V25-133BGC ROCHESTER

获取价格

 		ZBT SRAM, 256KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1354V25-133BGC CYPRESS

获取价格

 		ZBT SRAM, 256KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1354V25-166AC CYPRESS

获取价格

 		ZBT SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1354V25-166BAC CYPRESS

获取价格

 		ZBT SRAM, 256KX36, 3.5ns, CMOS, PBGA119, BGA-119
CY7C1354V25-200BAC CYPRESS

获取价格

 		ZBT SRAM, 256KX36, 3.2ns, CMOS, PBGA119, BGA-119
CY7C1354V25-200BGC CYPRESS

获取价格

 		暂无描述
CY7C135-55JC CYPRESS

获取价格

 		4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores

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