Datasheet > CY7C1297A

CY7C1297A

更新时间： 2024-01-22 23:55:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
13页	158K
描述
64K X 18 Synchronous Burst SRAM

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CY7C1297A 数据手册

297A

CY7C1297A/

GVT7164B18

64K X 18 Synchronous Burst SRAM

The CY7C1297A/GVT7164B18 SRAM integrates 65536 × 18

SRAM cells with advanced synchronous peripheral circuitry

and a two-bit counter for internal burst operation. All

synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

Features

• Fast access times: 9 and 10 ns

• Fast clock speed: 66 and 50 MHz

• Provide high performance 2-1-1-1 access rate

• Fast OE access times: 5 and 6 ns

• Single +3.3V –5% and +10% power supply

• 5V tolerant inputs except I/Os

• Clamp diodes to V_SSQat all inputs and outputs

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

inputs

include

all

addresses,

all

data

inputs,

address-pipelining Chip Enable (CE), depth-expansion Chip

Enables (CE2 and CE2), Burst Control inputs (ADSC, ADSP,

and ADV), Write Enables (WEL, WEH, and BWE), and Global

Write (GW).

Asynchronous inputs include the Output Enable (OE), Burst

Mode Control (MODE), and Sleep Mode Control (ZZ). The

data outputs (DQ), enabled by OE, are also asynchronous.

• Three chip enables for depth expansion and address

pipeline

Addresses and chip enables are registered with either

Address Status Processor (ADSP) or Address Status

Controller (ADSC) input pins. Subsequent burst addresses

can be internally generated as controlled by the Burst Advance

pin (ADV).

• Address, data, and control registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst

sequence)

Address, data inputs, and Read controls are registered

on-chip to initiate self-timed Write cycle. Write cycles can be

one or two bytes wide as controlled by the Read control inputs.

Individual byte enables allow individual bytes to be written.

WEL controls DQ1–DQ8 and DQP1. WEH controls

DQ9–DQ16 and DQP2. WEL and WEH can be active only with

BWE being LOW. GW being LOW causes all bytes to be

written.

• Automatic power-down for portable applications

• High-density, high-speed packages

• Low-capacitive bus loading

• High 30-pF output drive capability at rated access time

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced

double-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high-valued

resistors.

The CY7C1297A/GVT7164B18 operates from a +3.3V power

supply. All inputs and outputs are TTL-compatible. The device

is ideally suited for 486, Pentium®, 680 × 0, and PowerPC™

systems and for systems that benefit from a wide synchronous

data bus.

Selection Guide

7C1297A-66

7164B18-9

7C1297A-50

7164B18-10

7C1297A1-50

7164B18-12

Unit

Maximum Access Time

9.0

240

10.0

240

10.0

240

Maximum Operating Current

Maximum CMOS Standby Current

Cypress Semiconductor Corporation

Document #: 38-05204 Rev. *A

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised January 19, 2003

12 3 4 5 6 7...13

中文翻译

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与CY7C1297A相关器件

型号	品牌	获取价格	描述	数据表
CY7C1297A1-50AC	CYPRESS	获取价格	64K X 18 Synchronous Burst SRAM
CY7C1297A1-50AXC	CYPRESS	获取价格	Standard SRAM, 64KX18, 10ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1297A-50AC	CYPRESS	获取价格	64K X 18 Synchronous Burst SRAM
CY7C1297A-50AXC	CYPRESS	获取价格	Standard SRAM, 64KX18, 10ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1297A-66AC	CYPRESS	获取价格	64K X 18 Synchronous Burst SRAM
CY7C1297A-66ACT	CYPRESS	获取价格	Standard SRAM, 64KX18, 9ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1297A-66AXC	CYPRESS	获取价格	Standard SRAM, 64KX18, 9ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1297F	CYPRESS	获取价格	1-Mbit (64K x 18) Flow-Through Sync SRAM
CY7C1297F-117AC	CYPRESS	获取价格	1-Mbit (64K x 18) Flow-Through Sync SRAM
CY7C1297F-117ACT	CYPRESS	获取价格	暂无描述

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