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CY7C1297A-66ACT

更新时间： 2024-12-01 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
13页 158K
描述
Standard SRAM, 64KX18, 9ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1297A-66ACT 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.8
最长访问时间：9 nsJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：1179648 bit内存集成电路类型：STANDARD SRAM
内存宽度：18功能数量：1
端子数量：100字数：65536 words
字数代码：64000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：64KX18封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.1 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：14 mmBase Number Matches：1

CY7C1297A-66ACT 数据手册

 浏览型号CY7C1297A-66ACT的Datasheet PDF文件第2页浏览型号CY7C1297A-66ACT的Datasheet PDF文件第3页浏览型号CY7C1297A-66ACT的Datasheet PDF文件第4页浏览型号CY7C1297A-66ACT的Datasheet PDF文件第5页浏览型号CY7C1297A-66ACT的Datasheet PDF文件第6页浏览型号CY7C1297A-66ACT的Datasheet PDF文件第7页 
297A  
CY7C1297A/  
GVT7164B18  
64K X 18 Synchronous Burst SRAM  
The CY7C1297A/GVT7164B18 SRAM integrates 65536 × 18  
SRAM cells with advanced synchronous peripheral circuitry  
and a two-bit counter for internal burst operation. All  
synchronous inputs are gated by registers controlled by a  
positive-edge-triggered Clock Input (CLK). The synchronous  
Features  
• Fast access times: 9 and 10 ns  
• Fast clock speed: 66 and 50 MHz  
• Provide high performance 2-1-1-1 access rate  
• Fast OE access times: 5 and 6 ns  
• Single +3.3V –5% and +10% power supply  
• 5V tolerant inputs except I/Os  
• Clamp diodes to VSSQ at all inputs and outputs  
• Common data inputs and data outputs  
• Byte Write Enable and Global Write control  
inputs  
include  
all  
addresses,  
all  
data  
inputs,  
address-pipelining Chip Enable (CE), depth-expansion Chip  
Enables (CE2 and CE2), Burst Control inputs (ADSC, ADSP,  
and ADV), Write Enables (WEL, WEH, and BWE), and Global  
Write (GW).  
Asynchronous inputs include the Output Enable (OE), Burst  
Mode Control (MODE), and Sleep Mode Control (ZZ). The  
data outputs (DQ), enabled by OE, are also asynchronous.  
• Three chip enables for depth expansion and address  
pipeline  
Addresses and chip enables are registered with either  
Address Status Processor (ADSP) or Address Status  
Controller (ADSC) input pins. Subsequent burst addresses  
can be internally generated as controlled by the Burst Advance  
pin (ADV).  
• Address, data, and control registers  
• Internally self-timed Write Cycle  
• Burst control pins (interleaved or linear burst  
sequence)  
Address, data inputs, and Read controls are registered  
on-chip to initiate self-timed Write cycle. Write cycles can be  
one or two bytes wide as controlled by the Read control inputs.  
Individual byte enables allow individual bytes to be written.  
WEL controls DQ1–DQ8 and DQP1. WEH controls  
DQ9–DQ16 and DQP2. WEL and WEH can be active only with  
BWE being LOW. GW being LOW causes all bytes to be  
written.  
• Automatic power-down for portable applications  
• High-density, high-speed packages  
• Low-capacitive bus loading  
• High 30-pF output drive capability at rated access time  
Functional Description  
The Cypress Synchronous Burst SRAM family employs  
high-speed, low-power CMOS designs using advanced  
double-layer polysilicon, double-layer metal technology. Each  
memory cell consists of four transistors and two high-valued  
resistors.  
The CY7C1297A/GVT7164B18 operates from a +3.3V power  
supply. All inputs and outputs are TTL-compatible. The device  
is ideally suited for 486, Pentium®, 680 × 0, and PowerPC™  
systems and for systems that benefit from a wide synchronous  
data bus.  
Selection Guide  
7C1297A-66  
7164B18-9  
7C1297A-50  
7164B18-10  
7C1297A1-50  
7164B18-12  
Unit  
ns  
Maximum Access Time  
9.0  
240  
2
10.0  
240  
2
10.0  
240  
2
Maximum Operating Current  
Maximum CMOS Standby Current  
mA  
mA  
Cypress Semiconductor Corporation  
Document #: 38-05204 Rev. *A  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised January 19, 2003  
1234567...13

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