Datasheet > CY7C1297F

CY7C1297F

更新时间： 2024-02-24 21:08:10

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
15页	441K
描述
1-Mbit (64K x 18) Flow-Through Sync SRAM

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CY7C1297F 数据手册

CY7C1297F

1-Mbit (64K x 18) Flow-Through Sync SRAM

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the

first address in a burst and increments the address automati-

cally for the rest of the burst access. All synchronous inputs

are gated by registers controlled by a positive-edge-triggered

Features

• 64K x 18 common I/O

• 3.3V –5% and +10% core power supply (V_DD

• 3.3V I/O supply (V_DDQ

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

— 7.5 ns (117-MHz version)

)

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE₁), depth-expansion Chip Enables (CE₂and CE₃), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW_[A:B], and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

)

• Provide high-performance 2-1-1-1 access rate

The CY7C1297F allows either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects

an interleaved burst sequence, while a LOW selects a linear

burst sequence. Burst accesses can be initiated with the

Processor Address Strobe (ADSP) or the cache Controller

Address Strobe (ADSC) inputs. Address advancement is

controlled by the Address Advancement (ADV) input.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

• User-selectable burst counter supporting Intel^

Pentium^interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Supports 3.3V I/O level

• Offered in JEDEC-standard 100-pin TQFP

• “ZZ” Sleep Mode option

Functional Description^[1]

The CY7C1297F is a 131,072 x 18 synchronous cache RAM

designed to interface with high-speed microprocessors with

minimum glue logic. Maximum access delay from clock rise is

The CY7C1297F operates from a +3.3V core power supply

while all outputs may operate with either a +3.3V supply. All

inputs and outputs are JEDEC-standard JESD8-5-compatible.

Logic Block Diagram

ADDRESS

A0,A1,A

A[1:0]

MODE

ADV

CLK

BURST

COUNTER AND

LOGIC

CLR

ADSC

ADSP

B,DQPB

WRITE DRIVER

WRITE REGISTER

MEMORY

ARRAY

OUTPUT

BUFFERS

DQs

DQP

SENSE

AMPS

A,DQPA

DQA,DQPA

WRITE REGISTER

WRITE DRIVER

BWE

INPUT

REGISTERS

ENABLE

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05429 Rev. *B

Revised December 21, 2004

12 3 4 5 6 7...15

中文翻译

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与CY7C1297F相关器件

型号	品牌	获取价格	描述	数据表
CY7C1297F-117AC	CYPRESS	获取价格	1-Mbit (64K x 18) Flow-Through Sync SRAM
CY7C1297F-117ACT	CYPRESS	获取价格	暂无描述
CY7C1297H	CYPRESS	获取价格	1-Mbit (64K x 18) Flow-Through Sync SRAM
CY7C1297H-100AXC	CYPRESS	获取价格	1-Mbit (64K x 18) Flow-Through Sync SRAM
CY7C1297H-100AXI	CYPRESS	获取价格	1-Mbit (64K x 18) Flow-Through Sync SRAM
CY7C1297H-133AXC	CYPRESS	获取价格	1-Mbit (64K x 18) Flow-Through Sync SRAM
CY7C1297H-133AXI	CYPRESS	获取价格	1-Mbit (64K x 18) Flow-Through Sync SRAM
CY7C1298A	CYPRESS	获取价格	64K x 18 Synchronous Burst RAM Pipelined Output
CY7C1298A-100NC	CYPRESS	获取价格	64K x 18 Synchronous Burst RAM Pipelined Output
CY7C1298A-50NC	CYPRESS	获取价格	64K x 18 Synchronous Burst RAM Pipelined Output

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