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CY7C1292DV18-250BZXC PDF预览

CY7C1292DV18-250BZXC

更新时间： 2024-02-28 11:35:17
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
23页 990K
描述
9-Mbit QDR- II⑩ SRAM 2-Word Burst Architecture

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中文翻译

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CY7C1292DV18-250BZXC 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA, BGA165,11X15,40针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.8
Is Samacsys：N最长访问时间：0.45 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：250 MHz
I/O 类型：SEPARATEJESD-30 代码：R-PBGA-B165
JESD-609代码：e1长度：15 mm
内存密度：9437184 bit内存集成电路类型：QDR SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：165
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：1.5/1.8,1.8 V认证状态：Not Qualified
座面最大高度：1.4 mm最大待机电流：0.28 A
最小待机电流：1.7 V子类别：SRAMs
最大压摆率：0.6 mA最大供电电压 (Vsup)：1.9 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：13 mmBase Number Matches：1

CY7C1292DV18-250BZXC 数据手册

 浏览型号CY7C1292DV18-250BZXC的Datasheet PDF文件第2页浏览型号CY7C1292DV18-250BZXC的Datasheet PDF文件第3页浏览型号CY7C1292DV18-250BZXC的Datasheet PDF文件第4页浏览型号CY7C1292DV18-250BZXC的Datasheet PDF文件第5页浏览型号CY7C1292DV18-250BZXC的Datasheet PDF文件第6页浏览型号CY7C1292DV18-250BZXC的Datasheet PDF文件第7页 
CY7C1292DV18  
CY7C1294DV18  
9-Mbit QDR- II™ SRAM 2-Word  
Burst Architecture  
Features  
Functional Description  
• Separate Independent Read and Write data ports  
The CY7C1292DV18 and CY7C1294DV18 are 1.8V  
Synchronous Pipelined SRAMs, equipped with QDR™-II  
architecture. QDR-II architecture consists of two separate  
ports to access the memory array. The Read port has  
dedicated Data Outputs to support Read operations and the  
Write Port has dedicated Data Inputs to support Write opera-  
tions. QDR-II architecture has separate data inputs and data  
outputs to completely eliminate the need to “turn-around” the  
data bus required with common I/O devices. Access to each  
port is accomplished through a common address bus. The  
Read address is latched on the rising edge of the K clock and  
the Write address is latched on the rising edge of the K clock.  
Accesses to the QDR-II Read and Write ports are completely  
independent of one another. In order to maximize data  
throughput, both Read and Write ports are equipped with  
Double Data Rate (DDR) interfaces. Each address location is  
associated with two 18-bit words (CY7C1292DV18) or 36-bit  
words (CY7C1294DV18) that burst sequentially into or out of  
the device. Since data can be transferred into and out of the  
device on every rising edge of both input clocks (K and K and  
C and C), memory bandwidth is maximized while simplifying  
system design by eliminating bus “turn-arounds.”  
— Supports concurrent transactions  
• 250-MHz clock for high bandwidth  
• 2-Word Burst on all accesses  
• Double Data Rate (DDR) interfaces on both Read and  
Write ports (data transferred at 500 MHz) @ 250 MHz  
• Two input clocks (K and K) for precise DDR timing  
— SRAM uses rising edges only  
• Two input clocks for output data (C and C) to minimize  
clock-skew and flight-time mismatches  
• Echo clocks (CQ and CQ) simplify data capture in  
high-speed systems  
• Single multiplexed address input bus latches address  
inputs for both Read and Write ports  
• Separate Port Selects for depth expansion  
• Synchronous internally self-timed writes  
• Available in x 18 and x 36 configurations  
• Full data coherency, providing most current data  
Depth expansion is accomplished with Port Selects for each  
port. Port selects allow each port to operate independently.  
• Core VDD = 1.8V (±0.1V); I/O VDDQ = 1.4V to VDD  
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)  
• Offered in both lead-free and non-lead free packages  
All synchronous inputs pass through input registers controlled  
by the K or K input clocks. All data outputs pass through output  
registers controlled by the C or C (or K or K in a single clock  
domain) input clocks. Writes are conducted with on-chip  
synchronous self-timed write circuitry.  
• Variable drive HSTL output buffers  
• JTAG 1149.1 compatible test access port  
• Delay Lock Loop (DLL) for accurate data placement  
Configurations  
CY7C1292DV18 – 512K x 18  
CY7C1294DV18 – 256K x 36  
Selection Guide  
250 MHz  
200 MHz  
200  
167 MHz  
167  
Unit  
MHz  
mA  
Maximum Operating Frequency  
Maximum Operating Current  
250  
600  
550  
500  
Cypress Semiconductor Corporation  
Document #: 001-00350 Rev. *A  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 20, 2006  
[+] Feedback  
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CY7C1292DV18-250BZXC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1292DV18-167BZI CYPRESS

功能相似

 9-Mbit QDR- II⑩ SRAM 2-Word Burst Architectur
CY7C1292DV18-167BZC CYPRESS

功能相似

 9-Mbit QDR- II⑩ SRAM 2-Word Burst Architectur

与CY7C1292DV18-250BZXC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1292DV18-250BZXI CYPRESS

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 		9-Mbit QDR- II⑩ SRAM 2-Word Burst Architectur
CY7C1292DV18-300BZC CYPRESS

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 		QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165
CY7C1292DV18-300BZI CYPRESS

获取价格

 		QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165
CY7C1292DV18-300BZXC CYPRESS

获取价格

 		QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
CY7C1292DV18-300BZXI CYPRESS

获取价格

 		QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
CY7C1294DV18 CYPRESS

获取价格

 		9-Mbit QDR- II⑩ SRAM 2-Word Burst Architectur
CY7C1294DV18-167BZC CYPRESS

获取价格

 		9-Mbit QDR- II⑩ SRAM 2-Word Burst Architectur
CY7C1294DV18-167BZI CYPRESS

获取价格

 		9-Mbit QDR- II⑩ SRAM 2-Word Burst Architectur
CY7C1294DV18-167BZXC CYPRESS

获取价格

 		9-Mbit QDR- II⑩ SRAM 2-Word Burst Architectur
CY7C1294DV18-167BZXI CYPRESS

获取价格

 		9-Mbit QDR- II⑩ SRAM 2-Word Burst Architectur

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